Application Notes

Changes to the Capture-to-Allegro netlist process with OrCAD Capture v9.2.1 and later
Source: Cadence Engineering, Jeanine Potts & Moji Friedhoff, December 2001
Edited by: Dade Cariaga, January, 2002

This document explains the differences in deriving an Allegro netlist with OrCAD Capture v9.2.1 and later from previous versions. The new process involves several stages: preparing your Capture design for use with the new netlist tool, assigning specific Allegro properties, and, finally, generating the netlist.

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Introduction
Prior to Capture v9.2.1 (v9.2.1), generating an Allegro netlist in Capture was more of a haphazard process, involving a third-party netlist tool. However, with v9.2.1, Capture employs a new netlist tool that takes away many of the ambiguities that existed in previous version. Capture now has the capability to produce fully integrated Allegro netlists. For those familiar with the previous third-party netlister, the limitations in back annotation, ECO cycle process, trouble with passing properties to Allegro, and inability to add properties are gone. Further, Capture now includes cross-probing and cross-selection with Allegro.

Preparing your OrCAD Capture design for netlisting to Allegro
This section discusses how to prepare your Capture design to produce an Allegro netlist. This includes an explanation of how to apply device properties included in existing designs.

Setting the DEVICE property to map devices to Allegro footprints Previous to Capture v9.2.1, the (third-party) Allegro netlister created device files describing each component in your design. Capture used the DEVICE property to name the text file for each device. Parts that used the same DEVICE property value were included in the same device file. So, for example, all parts with the DEVICE property value of "RES1_4" were represented by the same text file. If a part did not include the DEVICE property, Capture attempted to use the component's Value property for the device file name.

The new Allegro netlist tool (available with Capture v9.2.1 and later) works somewhat differently. Now, if a DEVICE property exists on your parts when you generate an Allegro netlist., the parts are grouped according to the values of the DEVICE property. The netlister compares this grouping against the component definition properties. The properties used in this comparison are set up in the [ComponentDefinitionProps] section of your Allegro.CFG file. These are typically the Source Package, PCB Footprint, and Value properties. If the grouping of parts using the component definition properties is different than the grouping created by the DEVICE property you will get the ALG0013 error.

Error[ALG0013] Conflicting values of following properties found on different sections of <Part Reference>

For example, say you have three resistors, with Value property values of 1K, 10K, and 100K on your design. All three of the resistors have a DEVICE property value of RES. In this case, the netlist operation will fail with an ALG0013 error. This is because the DEVICE property groups all of these resistors together while the component instance properties group them separately since they have three different Value properties. If you remove the DEVICE property or modify it so that each resister has a unique DEVICE property value, Capture can generate the netlist successfully.

The DEVICE property exists within Allegro to set the primitive name for the components. If you do not have a DEVICE property on your parts in Capture, the netlister creates primitive names for those parts that are concatenations of the component definition properties that are listed in the allegro.cfg file. In Allegro, on each part there is a property called "Device Type" or "Primitive." This will be either the DEVICE property value or the aforementioned concatenation.

To remove the DEVICE property, in Capture, highlight the name of your design in the Design Resources folder of the Project Manager. Then choose the Browse Parts command. Capture prompts you to select either instances or occurrences to edit. If your design is a flat design, or a simple hierarchy, choose the preferred mode. If your design is a complex hierarchy, choose the preferred mode. Capture then displays the Browse Parts dialog box. Highlight all the reference designators in the left hand column. Press CTRL + E or choose Properties from the Edit menu. Capture displays a browse spreadsheet. This spreadsheet provides a method for editing properties for all the parts on the design. Select the entire column for the DEVICE property and click the Remove button.

If the DEVICE property was added in the library definition of the part, you must remove the property from the library parts. Run replace cache with the "preserve properties" option checked. Then delete the properties off the part instances in the design as described above.

In Capture v9.2.3 there is an environmental variable that can turn the DEVICE property off. This variable, IGNORE_PROP, is discussed later in this document.

Pin and gate considerations for migrating from OrCAD Capture to Allegro
You can assign part and net properties in Capture that will then be migrated to Allegro as a part of the Capture-Allegro netlist. You can also specify pins, gates, or packages in your PCB design for swapping in order to improve board routing.

Gate and pin swapping for multiple part packages

In Capture, when you place parts from multiple part packages on your schematic, any unused parts in that package that are not placed on the schematic are not included in the netlist by default. However, when Allegro generates a netlist for back annotation to Capture, any such unused parts are included in the back annotation data. This results in an error during the back annotation. To avoid this problem any unused parts should be placed on the schematic and specified as unconnected before you generate the netlist.

Note that, in order to allow gate and pin swapping for multiple part packages in Allegro, you must include all parts of the package in your Capture design.

Packaging of multi-section heterogeneous parts
In Capture v9.2.1, the netlister failed whenever it encountered a section of a heterogeneous part package that had no pins other than "Power" pins. The netlister generated the following error message:

Error [ALG0053] All pins are power < Part Reference >: <Schematic> , <Page> (<LocationX> , <LocationY)>

However, if there were at least one pin in the section that was defined as a non-power pin (for example, an "Input" pin) the netlist would be generated successfully.

In Capture v9.2.2 ISR and later, there is no such restriction.

Note that Capture v9.2.3 includes a property, "SPLIT," that, when its value is set to "True," and it is assigned to a heterogeneous part package, indicates that Allegro allows pin swaps between the various parts in the package. Please refer to the appropriate section later in this document.

Power pins: visible versus invisible
Any homogeneous multiple part packages in your Capture design must maintain consistency with regard to power pin visibility across all sections of that part. If some sections of the part have invisible power pins while other sections have visible power pins, you could see the following errors when you attempt to generate an Allegro netlist: In short, homogeneous multiple part packages must have all power pins either visible or invisible (not both) in order for the netlister to function properly.

In Capture v9.2 and previous versions, it was possible to have parts with multiple visible power pins of the same name (including parts in the Capture libraries). With v9.2.1 and v9.2.2, the Allegro netlister (because of a development oversight) did not support this, and you might have encountered the following error message when attempting to netlist:

#1 Error [ALG0050] Duplicate Pin Name "VCC" found on Package 4 HEADER_0 , J1: SCHEMATIC1, PAGE1 (4.60, 0.90)

Note that only visible power pins must have unique names. Duplicating names for invisible power pins, will not cause problems during netlist creation.

The special Capture ISR release v9.2.2 addresses this problem by appending a pin number to the pin name in the following format:

<pin name>#<pin number>

Though the pin names are manipulated, all pins with the same names will be connected to the same power net. So, for example, assume a part has two pins named VCC: pin 14 and pin 28. When the netlist is created, these pins are stored in the information files as VCC#14 and VCC#28. However, both pins are connected to a single net, VCC.

Also, while cross-probing between Capture and Allegro is fully functional, when you select a power pin that is part of a power net in Allegro, the corresponding net (as opposed to pins) in Capture is highlighted.

Lastly, there is a limit to the length of power pin names for Capture-Allegro netlisting. All power pins on a part will be listed in the PSDCHIPS.DAT file on one line. In previous versions of 14.x release, if this line is over 1024 characters the netlist will not import into Allegro. You must manually edit the PSTCHIPS.DAT file such that each POWER_PINS line in the file is no longer than 1024 characters. (In Capture v9.2.3, this limit is increased to 2024 characters per line.)

PCB footprints and pin requirements for parts
In order to correctly map a logical package to the physical board environment, you must specify a PCB footprint for each and every part in your design. Allegro must have a valid PCB footprint property (stored in the *.PSM file) for each part so the netlister can assign this property in the PSTCHIP.DAT file as the JEDEC_TYPE. If this is missing the netlister will fail with an ALG0012 error.

[ALG0012] Property "PCB Footprint" missing from part <Part Reference>: <Schematic> , <Page> (<LocationX> , <LocationY)>

Capture allows parts with no pins to be created for items that you want in the bill of materials but not on the netlist. Mechanical parts, for example, have no pins. However, with Capture v14.x, including such parts in your design will cause errors when you attempt to import your Capture netlist into Allegro. Future Capture releases will address this restriction.

In Capture v9.2 (and prior releases), the Capture netlister ignored parts without pins, allowing symbols for mechanical parts to be added to the schematic for BOM purposes. The new Allegro netlister requires all parts on the schematic to have at least one pin and therefore a PCB footprint.

With Capture v9.2.3, the Allegro netlister requires that you assign an arbitrary footprint value to the mechanical parts, in order to create the netlist files. This will meet the requirements of the netlister for creating a bill of materials that includes these mechanical parts. Note that, when you generate the netlist for a design that includes these bogus footprint values, you will see the following warning:

#2 Warning [ALG0060] No pins are present in U?. Ignoring this component in netlist.

Illegal characters
There are a few characters that the netlister does not allow.

These are: In general, it is best to limit net, pin, and part names to the basic alphanumeric characters A-Z and 0-9. Illegal characters are replaced by an underscore (_). When this occurs, the netlister produces an ALG0051. Explanation points (!) cause fatal errors during netlisting (Error ALG0052).

Error [ALG0051] Pin is renamed to after substituting illegal characters on < Part Reference>: , ( ,

Error [ALG0052] Net has illegal Character "!". Please rename the net

New features of the Capture-Allegro netlister
The new version of the Capture-Allegro netlister includes several new features and methods.

Configuration file
The configuration file specifies net, part (function), component instance and component definition properties. This mapping determines which properties may be netlisted from Capture to Allegro or back annotated from Allegro to Capture. If a Capture property is not included in the configuration file it is not passed to Allegro. Similarly, if an Allegro property is not listed in the file, it does not get back annotated to Capture.

The configuration file is divided into four sections, written in a Windows .INI format.
  • ComponentDefinitionProps Allegro component definition properties, output in PSTCHIP.DAT
  • ComponentInstanceProps Allegro component instance properties, output in PSTSPRT.DAT
  • netprops Allegro net properties, output in the PSTXNET.DAT
  • functionprops Allegro function properties, output in the PSTXPRT.DAT
You can have many different configuration files. Specify which file you want to use in the Setup dialog box before netlisting.

A list of typical properties used with Allegro may be found in the Capture-Allegro filter of the property editor. This filter is built on the PREFPROP.TXT file, which is copied to your Capture directory during installation.

User-defined properties
All user-defined properties must be named using all uppercase characters. If you do not see user-defined properties in the netlist or the back-annotation, it could be that the property names are misspelled or not all uppercase. Check the ALLEGRO.CFG file to determine which properties you are passing to Allegro. Properties defined with lower case letters in the property name do not get transferred to the board in Allegro. For example: R1 has a room property of 2, R2 has a ROOM property of 6. On the board file only R2 has a Room Property. No message is created when a property is not recognized.

Assigning no connect pins for Allegro
Previous to Capture v9.2.3, the netlister accounted for no connect pins by calculating the actual number of pins on the required package from the number of schematic pins placed and the number of no connect pins supplied from the database. Using the new netlister, if the design contains parts with no unconnected pins there are no issues. Also, if the design contains parts with unconnected pins and these pins are listed in the NC properties on their respective parts there are no issues.

Do not use a combination of these methods in your design, or you will encounter problems creating the netlist.

The ALLEGRO.CFG file does not need to have a NC=YES line added because the NC property is hard coded in the netlister. NC_PINS is an alternate property name, NC is treated as NC_PINS. The number of pins specified in the PSTCHIP.DAT file must equal the number of pins specified in the Allegro footprint. The total number of pins found in PSTCHIP.DAT includes regular pins, power pins, and NC (no-connect) pins if present. If you have numbered through-hole pins or non-electrical pins that you are not connecting on the board then you must do one of the following to the part in your design:
  • Add an NC property to the part. For the value of the NC property, use the pin numbers of the non-electrical pins separated by commas. For example, if you had an 8-pin footprint with the two through-holes being pins 7 and 8, then you would have a 6-pin part on your design with an NC property containing the value of "7,8." The netlister will produce an error message if there are missing pins on a symbol. After adding the NC property on a part, use the Update Design Cache command to update the part on the design (if you realize that the part is missing pin numbers while creating the netlist).
  • Place a No Connect symbol on pins that you don't want to be connected to anything. If you look in the property editor you will see a check in the "Is No Connect" pin property check box. In the design, you will see an X symbol on the pin. So, for the previous example you would have an 8-pin part in your design with No Connect on pins 7 and 8. Don't connect any nets to the non-electrical pins on the part. So, in the two examples above, you would have an 8-pin part with nothing connected on pins 7 and 8.
Do not use a combination of these two options on the same part or the netlister will issue a fatal error.

You must account for unconnected pins of multi-section parts, such as mounting holes of multi-row connectors. To do so, however, do not make the part heterogeneous with the mounting holes as pins on one section or distributed among the sections. Instead, make the part homogeneous and add a NC property to each section of the part, with the same pins listed for the NC property on all sections. In the part editor, you can add a NC property to each part in turn by choosing Previous Part from the View menu and placing the same NC property on all sections.

No connect pins in OrCAD Capture CIS
There are ways in the Part database to include information about the NC pins but not check it against the database. Basically, you can set up the part to have the NC property in the database but set up a "do not update" property in the CIS configuration file so that property is never checked against the database.

You may have the NC property set up in the database so that the component engineers, rather than the design engineers, can maintain the property 'correctly'. The CIS configuration is set to transfer this property to the design. You should turn off the Transfer Blank Properties to the design feature in the Capture CIS configuration file. This option is found under the Administrative Preferences tab of the CIS configuration window.

Assigning POWER_GROUP in Capture for use in Allegro
The POWER_GROUP property has been added with Capture v9.2.3 to control the connections of power pins for Allegro netlisting. This property does not change the connectivity for any other netlist formats.

POWER_GROUP is a special component definition property that lets you modify the POWER_PINS property at the schematic instance level to reassign power net connectivity. The POWER_PINS property is a derived property from pin type "POWER". The two properties POWER_GROUP and POWER_PINS are treated as a property pair and are evaluated at the same level.

The subtype name is optional. For example, assume you have an instance of a part with various power signals VCC, VDD, VPP, and VSS. If you want all these signals to be shorted to VCC, then assign the following POWER_GROUP property in the Attribute form in Capture property spreadsheet:

POWER_GROUP = VDD=VCC;VPP=VCC;VSS=VCC

Example
on the Part on Schematic Instance in the pstchips file
Pin numbers of VCC are 14,28 and GND are 7,21. POWER_GROUP=VCC=VDD; POWER_PINS='(VDD:14,28)'; POWER_PINS='(GND:7,21)';


For most properties, you can only have one occurrence of a property at any level. POWER_GROUP is an exception (along with NC_PINS and POWER_PINS); you can have multiple occurrences of this property in the PSTCHIPS.DAT files and on schematic instances.

Another example: The U1 instances have invisible power pins VCC, VDD, GND, AGND. The netlister connects these power pins to global nets VCC, VDD, GND, AGND by default. Suppose, however, that you want to connect VDD to AVDD and AGND to GND. In this case, go to the instance property of that component and add POWER_GROUP = VDD=AVDD;AGND=GND. The netlister will automatically connect VDD, AGND to AVDD,GND.

The online help has more information about this. To find it, search for POWER_PINS in the index.

How to use the SPLIT property to perform a pin swap between parts in a heterogeneous package
With Capture v9.2.3 there is a property, "SPLIT," that, when its value is set to "True," and it is assigned to a heterogeneous part package, indicates that Allegro allows pin swaps between the various parts in the heterogeneous package. Note that Capture defines heterogeneous packages as packages comprised of non-identical parts.

The SPLIT property is applied only to heterogeneous parts. Allegro treats homogeneous multipart per package parts as a single function allowing pin or gate swaps. Heterogeneous multipart per package parts, on the other hand, are treated as multisection parts allowing pin swaps within a section (only). When the SPLIT property is assigned to the sections of a heterogeneous multipart package, Allegro allows pin and gate swapping between all parts of the package, regardless of section.

SPLIT takes two values "TRUE" and FALSE" (default). This property is a part property/instance level property. It can be added to a part in the library editor or even at the instance level of a schematic. To add this property at the library level, open the library part in library editor and go to Options -> Part Properties. Add a new property called SPLIT and set its value as "TRUE". Note that you must add this property on all the parts (sections) of the package. Note that this is the preferred method for using the SPLIT property.

To add this property at the instance level, select the part on the schematic sheet then select Edit Properties. The Property spreadsheet appears. Add a new column to the spreadsheet, using SPLIT as the property. Be sure to include a value.

When you create a Capture-Allegro netlist, the netlister generates a flat netlist for the parts that include the SPLIT property (where the value is "TRUE)." This results in Allegro interpreting the part as single section, rather than multisection. This allows you to perform pin swapping across sections of the part. Note, however, that cross probing on pins will not work for such parts. Instead, you can perform cross-probing on the associated nets to determine pins.

When using the SPLIT property, keep these things in mind:
  • You must add the SPLIT property to each and every section/part of the package.
  • You should understand that this property wouldn't work on homogeneous (symmetrical) or asymmetrical parts. Currently, there is no tool for detecting if you have erroneously placed the SPLIT property, so be sure to apply the property to only valid parts.
  • There must not be any duplicate pins across the sections/parts of a split package.
Ignore property
In Capture v9.2.3 there is an environmental variable that can turn the DEVICE property off. To ignore the device property on all designs, define the IGNORE_PROP property as an environmental variable/system variable. Assign IGNORE_PROP the value "DEVICE". Once the IGNORE_PROP is set up as an environmental variable, the netlister will ignore the DEVICE property.

To add a system variable:

Access this through the Start button. Then choose Settings, Control Panel. Double click on the System icon and choose the Environment tab.

Type the Variable name as IGNORE_PROP and the Value as DEVICE.

Press OK and restart Capture for the new environmental variable setting to be applied.

If IGNORE_PROP is defined as a user environmental variable, it is login specific. To define this as system variable, you need to have administrative privileges on your computer. After defining this variable, you need to re-open Capture to read in the new environmental variables.

Netlist error checking with OrCAD Capture v9.2.3
The netlister has an Allegro specific error checking mechanism that generates a list of Allegro formatting errors (if any) and halts the netlist generation. The error messages are written to the session log. If there are no errors, the netlister generates the PST*.DAT files.

The following is a list of errors that may appear during Capture-Allegro netlist generation:

DRC Error Number Description
ConflictPowerPinConnect ALG0045 Power pins on a homogeneous multiple parts per package part are repeated between sections and wired up to different nets.
dupPinName ALG0051 If pins have duplicate names then a number sign (#) and the pin number are appended to the name to make them unique for the Allegro netlist. This is a warning.
pinNumberMissing ALG0031 Pins need to have numbers. Even if they have names defined for the pin it needs a number too.
dupPinNumber ALG0045 A pin number is used more than once on a part.
conflictPowerPinVisible ALG0044 Power pins on a homogeneous multiple parts per package part are visible on one section and not visible on one of the other sections. Having this different property setting on parts keeps the sections from packaging together as one physical part for Allegro.
dupNCPinNumber ALG0049 No connect pin defined both by including the pin number in the NC property and by placing no connect symbols.
partsPerPackage ALG0045, ALG0013, ALG0014 The sections sharing the same reference numbers are not from the same source part and cannot be packaged together. These errors can arise when manually setting the reference designators on multiple parts per package parts.
missingPCBFoot ALG0012 Missing symbol value (*.PSM) in the PCB Footprint property for this part.
illegalNetChar ALG0015, ALG0052 Illegal characters are used in a net name. The warning ALG0015 replaces some characters with an underscore. Other characters, like the explanation point, cause the netlister to fail and generate the ALG0052 error. Avoid using special characters. At this time Allegro permits these non-text characters in net names: #%&()*+-./>?@[]^_`| The design rule check only looks at the final net name used in the netlist. It does not check all net aliases for legal characters.