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 24 Jan 2006, 10:50 PM
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jim2000
Joined on 01-14-2006
Posts 105
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The fanout and Capacitors
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Hi,
I am Jim. I met with sometrouble. When I fanout the power and ground, I could fanout, but I couldn't use a capacitor in the power pin. If I connect a capacitor to the power pin, it always show me "bad pad exit". If I first fanout, then I put a capacitor, the via will miss at this time(I guess that in one layer, the system would cancel the via). If I use autofanout, I found that I couldn't get satisfaction.
Thank you very much!
Jim
Forum: Power Nets & Pins
Posted: : Saturday, December 3, 2005 5:58 AM [GMT -5]
Post Subject: : Re: Route between two SMD Pins Kixx wrote: | Hi @cseltzer,
thanks that was it.
Kixx |
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25 Jan 2006, 11:54 AM
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Ron_O
Joined on 09-03-2002
Thorndale, Canada
Posts 1,570
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Re: The fanout and Capacitors
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Not sure I follow your problem exactly but sounds like you have vias that are disappearing when you route. You could try using Freevias to prevent this -press the E key when you want to insert a freevia.
Ron O.
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25 Jan 2006, 9:12 PM
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jim2000
Joined on 01-14-2006
Posts 105
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Re: The fanout and Capacitors
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Thank you and I will try it. I have some other questions:
1. How can I use a pad I defined when I create a footprint.
2. Could I splite the power plane into 5 or 6 parts. For example, there are four different power on one chip: Logic or core level (1.8v), I/o drive level (3.3v), A/D level, D/A level, 2.5v level.
3. BGA fanout is too hard to fit. (I always use inchs in my board, when I fanout BGA, I found that I have to chang it into metric).
4. How could I define the size of free via (if it is defined in spreadsheet
->padstacks and spreadshet -> nets) when I use a free via in a net, it
automatic use that via .
Thanks and maybe more questions posted in tomorrow.
Jim
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26 Jan 2006, 2:37 PM
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Ron_O
Joined on 09-03-2002
Thorndale, Canada
Posts 1,570
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Re: The fanout and Capacitors
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1. How can I use a pad I defined when I create a footprint.
>> When you place the pad, right-click| Properties and change the Padstack Name
2. Could I splite the power plane into 5 or 6 parts. For example, there are four different power on one chip: Logic or core level (1.8v), I/o drive level (3.3v), A/D level, D/A level, 2.5v level.
>> You can. Just be careful you don't starve copper areas by making the splits too small in a via loaded area.
3. BGA fanout is too hard to fit. (I always use inchs in my board, when I fanout BGA, I found that I have to chang it into metric).
>> Make sure your via size (and BGA pad size) are optimized for the pad spacing. You may need to go to a finer grid (or 0 grid) to accurately place fanouts for a metric BGA in an imperial database.
4. How could I define the size of free via (if it is defined in spreadsheet
->padstacks and spreadshet -> nets) when I use a free via in a net, it
automatic use that via .
>> While in route mode, right-click and select Change Via Type. Or select via and right-click, change.
Ron O.
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OrCAD Community » OrCAD Community Forums » Basic PCB Design » The fanout and Capacitors
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