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 06 Dec 2003, 7:19 AM
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algaas
Joined on 10-14-2003
Posts 3
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Hello,
I have fanned out a bga component using the via under pad technique, using Layout Plus 9.20. The via i am using is a buried via, connecting TOP layer with IN1 layer. My layer stackup is like the following:
TOP
IN1
GND
...
When i make a DRC to the board, y obtain a lot of errors "Insufficient clearance on plane layers" on all the under pad vias, and i do not know why.
I would thank any suggestion, because it is very difficult to debug the board considering the huge amount of errors that i obtain after fanout.
Best Regards
Daniel.
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08 Dec 2003, 4:53 AM
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cseltzer
Joined on 06-11-2002
Largo, FL
Posts 853
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My first suggestion is to check the size of the pads on the plane layers. They need to be about 15 to 20 mils larger than the pads on the routing layers. In an earlier post someone gave a formula for calculating the size of the "antipad".
Chris Seltzer
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08 Dec 2003, 8:37 AM
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Ron_O
Joined on 09-03-2002
Thorndale, Canada
Posts 1,570
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If you assigned your stackup in the Layers spreadsheet just as you noted:
TOP
IN1
GND
and continue to get errors, it may be due to a bug in blind and buried vias processing. A previous post (by an Orcad rep it appears) mentions this -see:
http://www.designpcb.com/discuss/user/non-frames/message.asp?forumid=12&messageid=3196&ar=
for more details. If above link doesn't work do search on 'blind' and see post 02/11/03.
Ron.
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09 Dec 2003, 8:45 AM
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algaas
Joined on 10-14-2003
Posts 3
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Thank you Ron and Chris for your answers,
I think that Ron is right, because my physical layer order is TOP, IN1,.. and the buried via that causes the DRC problems is defined only in these layers. Hence, is a nosense to give an "Insufficient Clearance on plane layers" error when these vias are not passing through any plane.
If it is a bug in the program there is little to do about that, maybe a patch will solve it. My orcad version is 9.20
Best Regards
Daniel.
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11 Dec 2003, 2:22 PM
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stan
Joined on 01-07-2003
Posts 23
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This is fixed in release 10.0 but for a workaround in previous releases, temporarily remove the pad definition on the DRL layer for your blind and buried vias before running the DRC.
-Stan
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14 Dec 2003, 9:05 AM
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algaas
Joined on 10-14-2003
Posts 3
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Hello Stan,
In fact this is a temporal solution. I have removed the DRILL and DRLDWG definitions from the Padstacks spreadsheet for the blind and buried vias and then passed the DRC, and the "Insufficient clearance on plane layer" errors are gone. After that, I fixed the true errors of the design and then restore the drill definition for the B&B vias.
Thank you very much indeed for your answer.
Daniel.
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28 May 2004, 2:09 AM
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zoom
Joined on 05-15-2003
Posts 33
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I've got the same problem, but the "workaround" doesn't really help! Instead of 1500 "insufficient clearance on plane..." errors, I've got 600 "bad net continuity" errors. The reason is clear: If the drills are undefined it couldn't be connected! Thats really a mess because installing the V10 brings a lot of other bugs which makes work impossible! It's time to change.
Jo
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20 Jul 2004, 7:02 AM
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natsmidas
Joined on 07-20-2004
Posts 1
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With ref ur layer stack, it is not burried via it is blind via.In this condition u can change ur plane layer into +ve plane (routing plane) ur DRC problem solved.
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OrCAD Community » OrCAD Community Forums » Routing with BGAs » Vias under pad
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