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Managing Constraints using Allegro Design Entry CIS with Allegro PCB Editor i

Overview

Allegro Properties Filter

Class Rules

Signal Integrity Rules

Differential Pairs

Propagation Delay

Relative Propagation Delay

Impedance

Passing Constraints to PCB Editor

Viewing Constraints in PCB Editor

Back Annotating Constraints

Summary

Overview

The purpose of this application note is to describe how you can enter signal integrity constraints into an Allegro Design Entry CIS database for use in the Allegro PCB editor.

 

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Allegro Properties Filter

All of the constraints discussed in this app note are accessed by editing properties on a net and selecting the Cadence Allegro filter.

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Class Rules

SPACING_CONSTRAINT_SET and PHYSICAL CONSTRAINT SET

SPACING_CONSTRAINT_SET defines the spacing rules between the net and other objects

-vias

-pins

-other nets

PHYSICAL CONSTRAINT SET defines the physical parameters for the net

-min max line width

-T points allowed

-Via types

In CIS only the CLASS is defined for a net. The parameters of the rule are then defined in Allegro PCB editor. To define the CLASS on a net edit it’s properties in the property editor.

The value of the property is a string, technically arbitrary in value, however a good practice is to assign the type to a pre-determined value that represents the rule

For example:

SPACING_CONSTRAINT_SET =10_mil_trace

PHYSICAL_CONSTRAINT_SET= critical_clock_net

The parameters of these rule sets would then be defined in Allegro PCB Editor.

A recommendation is to have a pre-determined set of rules defined between the EE and the PCB designer. This will allow the PCB designer to load in the rule definitions

Procedure

  1. Select a net on a page, or a group of nets by using block select.

  2. Edit properties on the selection.

  3. Switch the filter to Cadence_Allegro

  4. Fill in the value for the SPACING and PHYSICAL CONSTRAINT SET

  5. This can also be done by exporting all the net properties to a CSV file, then importing them back in with the new properties added.

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  6. The rules are passed to Allegro PCB editor as properties on the net

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Signal Integrity Rules

Electrical Constraint Set

Electrical Constraint Sets (ECSETS) are a collection of pre-determined electrical rules. Instead of defining specific constraint values for a net it can be classified with an Electrical Constraint set. The rules are then defined in the ECset in the Allegro Constraint Manager.

For example: Differential Pairs have several parameters, phase tolerance, secondary gap, primary gap, gather control…. Rather then defining each of these parameters on the net all of these parameters can be defined in an ECSET and the ECSET can be applied to the net.

In CIS the ECSET is defined for a net by adding the property ELECTRICAL_CONSTRAINT_SET to the net.

The value of the property is a string, technically arbitrary in value, however a good practice is to assign the type to a pre-determined value that represents the rule

For example:

Net Name            ECSET

Critical clock        Clock

DiffP+                  Diff_pair_50ohm

DiffP-                   Diff_pair_50ohm

Suggestions

  • Name nets that are going to be constrained.

  • Apply the SI constraint to the net attached to the driver pin.

    The xnet will inherit the constraint in Allegro when it is built.

  • Use pre-determined naming conventions for EC Sets

    • DDR2, CLS, DIFF_P_50ohm.

Procedure

  1. Select a net on a page, or a group of nets by using block select.

  2. Edit properties on the selection.

  3. Switch the filter to Cadence_Allegro

  4. Fill in the value for the ELECTRICAL_CONSTRAINT_SET

  5. This can also be done by exporting all the net properties to a CSV file, then importing them back in with the new properties added.

  6. In Allegro Constraint Manager define the parameters for the ECSET or load in an existing ECSET file

Differential Pairs

Defining nets as a Differential Pair causes them to be routed as such and applies Diff Pair spacing rules.

In ADE CIS a differential pair is created by adding the DIFFERENTIAL_PAIR property to two nets.

The value of the property is a string, technically arbitrary in value, however a good practice is to assign the type to a pre-determined value that represents the rule

For example:

Net Name DIFFERENTIAL_PAIR

Net1+ DP_Net1

Net1- DP_Net1

Notice that the two different nets have the same value for DIFFERENTIAL_PAIR

Procedure

Manual Diff Pair Creation

  1. Select the two nets that make up the diff pair

  2. Edit properties on the selection.

  3. Switch the filter to Cadence_Allegro

  4. Fill in the value for the DIFFERENTIAL_PAIR, assigning both nets the same value.

Automatic Diff Pair Creation

  1. Select tools create diff pair

  2. The dialog box will open

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  3. Select the nets in the left window to push them to the right window

  4. Type the name of the diff pair in the field.

    Hit Create. The diff pair is created. Repeat for other diff pairs.

  5. Select the Auto Setup button

    The form below opens

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  7. This form will automatically build differential pairs provided nets in the design have a common + and – suffix. Provide the + and – suffix used in the design, provide the desired prefix and all nets with the naming convention will be turned into diff pairs and have the DIFFERENTIAL_PAIR property assigned

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Propagation Delay

Propagation delay controls the delay, in time or distance, for a signal to propagate from

driver to receiver.

Propagation Delay is a property attached to a net however the syntax is complicated so CIS has a UI to guarantee the correct syntax.

Procedure

  1. Select a net on a page, or a group of nets by using block select.

  2. Edit properties on the selection.

  3. Select the Allegro Signal Flow property filter

  4. Select the filed for the net and RMB -> invoke UI

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  5. The form below opens

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  6. Apply the values in the fields to define the Propagation delay required for the net.

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Relative Propagation Delay

Relative Propagation delay builds on Propagation Delay by forcing a group of nets to have the same Propagation Delay

Relative Propagation Delay is a property attached to a net however the syntax is complicated so CIS has a UI to guarantee the correct syntax.

Procedure

  1. Select a net on a page, or a group of nets by using block select.

  2. Edit properties on the selection.

  3. Select the Allegro Signal Flow property filter

  4. Select the filed for the net and RMB -> invoke UI

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  5. The form below opens

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  6. Define the Match Group name (1). Specify the pin pairs(2). Then set it as the target net (3)

  7. To add other nets to this match group. Repeat steps 1-5 then,

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  8. Select the Match Group (4); define the RPD rules for the net(5). The members of the match group are also displayed on the right.

  9. Hitting ok results in the correct value for the RELATIVE_PROPAGATION_DELAY property value

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Impedance

Impedance is defined for a net by adding the property IMPEDANCE_RULE

CIS does not have a UI to ensure the correct syntax. The correct syntax is

Driver: Receiver: Target units: Tolerance

For example

ALL:ALL:50 ohm:2 %

This means All Drivers to All Receivers must be 50 ohm +/- 2%

Procedure

  1. Select a net on a page, or a group of nets by using block select.

  2. Edit properties on the selection.

  3. Select the Allegro property filter

  4. Add the desired impedance value to the net. The format is Driver:Receiver:Target units: Tolerance

    For example ALL:ALL:50 ohm:2 %

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Others

  • TESTPOINT_QUANTITY

    • Defines the number of test points that need to be generated.

  • MAX VIA COUNT

    • Limits the number of vias on a net

  • RATSNEST_ SCHEDULE

    • MIN_TREE indicates that the net rat should be displayed with the

      minimum spanning tree algorithm. This can form Ts at pins.

    • MIN_DAISY_CHAIN indicates that a minimum length daisy-chain schedule is formed.

    • SOURCE_LOAD_DAISY_CHAIN indicates that a source-to-load ECL daisy-chain schedule is used.

    • FAR_END_CLUSTER automatically places a single Tpoint in a schedule at a calculated location.

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Passing Constraints to PCB Editor

All of the properties mentioned will be passed to PCb Editor into the Constraint Manager when Allegro PST netlist are generated.

Procedure

  1. Select the .DSN file in the project manager

  2. Under tools ->create netlist

  3. Select the PCB Editor tab the form below opens

     

    This form is used to create the Allegro netlist files and load them into an Allegro database.

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Allegro.cfg

Hitting Setup opens the Allegro.cfg file. The Allegro.cfg file controls which properties get passed to Allegro. A default Allegro.cfg is located in<installation dir>/tools/Capture All the constraints mentioned here are included in the default. The Allegro.cfg is a text file. An example segment is below.

 

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4. Select the option to create the PCB Editor Netlists.  This creates three netlist files

PSTCHIP.DAT

PSTXNET.DAT

PSTXPRT.DAT

and puts them in an Allegro subdirectory in the working dir.

5.  If desired the netlist can also be loaded into Allegro by enabling the “Create or update PCB” option 

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Viewing Constraints in PCB Editor

Once the netlist is loaded into PCB Editor, Constraint Manager can be launched to view the constraints.

Differential Pairs defined in CIS

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Relative Propagation Delay defined in CIS

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XNets

An Xnet is the entire connection from driver to receiver. Many SI constraints are applied to an Xnet rather then individual nets. This picture shows the difference between a NET and an Xnet

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CIS does not have the ability to recognize Xnets. Only net object properties are applicable in CIS

Once Signal Models are assigned to discrete parts in Allegro Xnets are created. Once Xnets are created they will inherit any constraint assigned to a net object passed in via the PST netlists.

New constraints assigned to an Xnet results in the net object members of the Xnet to inherit the constraints. Inherited constraints are NOT back annotated.

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Back Annotating Constraints

Back Annotation extracts data from the Allegro brd file, netlists the schematic, compares the differences and creates a swap file. The swap file is then applied to the CIS design file. There are several files involved in this process

  1. The CIS .dsn design file

  2. The *.PST netlist files generated from the design.

  3. The *VIEW.dat files generated from Allegro

  4. The Allegro.cfg file.

  5. The PxlBa.txt file. This file dictates the properties extracted from Allegro.

Allegro looks for this file in the current working directory. If it is not found there, it looks for it in <installation dir>/tools/pcb/text/views

Procedure

  1. Select the .dsn file in the project manager

  2. Select tools->back annotate. The UI below opens

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  3. Select Generate Feedback Files. This extracts the *view.dat files from Allegro.

  4. Select the Allegro Board file

  5. The Back Annotation choices allow for viewing the changes and applying the changes.

  6. Verify the updates from Allegro

This is an example section from the swap file. This example shows two nets with a new impedance rule.

Section2 UpdateProperties Nets UppercaseCombined

"{Net Name}"            "IMPEDANCE_RULE"

"NET_1"                   "ALL:ALL:20 ohm:2 %"

"NET_2"                   "ALL:ALL:20 ohm:2 %"

.End

These updates will become Net Properties in CIS.

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Summary

Signal integrity constraints can be managed in the CIS to PCB Editor flow by entering them

as net level properties in the CIS property editor and passing them to Allegro via the .pst netlist. Net level constraints can be modified in Allegro and then back annotated to CIS.