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OrCAD Flow Tutorial



Introduction to the tutorial

Creating a schematic design

Simulating a design

Board design using OrCAD PCB Editor

Glossary




Introduction to the tutorial

This chapter consists of the following sections:

Objective of the tutorial

To enable users to evaluate the power of the OrCAD PCB tools used in the Windows-based PCB design process. You can use this tutorial to perform all the steps in the PCB design process. The tutorial focuses on the sequence of steps to be performed in the PCB design cycle for an electronic design, starting with capturing the electronic circuit, simulating the design with PSpice, through the PCB layout stages, and finishing with the processing of the manufacturing output and maintaining the design through ECO cycles.

Tasks covered in this tutorial may not cover all the features of a tool. In this tutorial, the emphasis is on the steps that you will need to perform in each OrCAD tool so that your design works smoothly through the flow.

Audience

This tutorial is useful for designers who want to use OrCAD tools for the complete PCB design flow or for analog simulation flow.

You can also benefit from the tutorial if you are a first-time user of OrCAD Capture, PSpice, OrCAD PCB Editor, or OrCAD PCB Router.

Using the tutorial

To run through the complete tutorial, you need the design example and following tools:

  • OrCAD Capture
  • PSpice A/D
  • OrCAD PCB Editor
  • OrCAD PCB Router

All these tools are available in the OrCAD PCB Designer with PSpice.

This tutorial does not cover the tasks included in Capture CIS.

Installing design example

Unzip the flowtut.zip file provided with this tutorial.

The design files are available at <installation_directory>/doc/flowtut/tutorial_example.

When you expand the design, the following directory structure will be created.

The partial directory contains files generated at the end of Chapter 2, “Creating a schematic design.” Use the files in this directory only if you want to skip the design creation steps covered in Creating a schematic design and directly move to the later chapters.

The complete directory contains all the files generated through all the chapters in this tutorial. You can use the files in the complete directory to verify your results.

Terminology

OrCAD Capture
Capture (initial CAPS)

OrCAD’s schematic design tool

The terms OrCAD Capture and Capture have been used interchangeably in the tutorial.

PSpice

OrCAD’s simulation tool, used for simulating both Analog and digital circuits.

OrCAD PCB Editor
PCB Editor

OrCAD tool used for PCB routing and floor-planning.

The terms OrCAD PCB Editor and PCB Editor have been used interchangeably in the tutorial.

What’s next

In the next chapter, Creating a schematic, you will use OrCAD Capture for creating a schematic design. You will learn to perform basic design tasks such as adding components from a library, adding wires, and getting your design ready for simulation.

Recommended reading

For information about individual tools, see the respective user guide.

TOC




Creating a schematic design

This chapter consists of the following sections:

Objective

To create a schematic design in OrCAD Capture. In this chapter, you will be introduced to basic design steps, such as placing a part, connecting parts using wires, adding ports, generating parts, and so on.

The steps for preparing your design for simulation using PSpice and for taking your design for placement and routing to the PCB board layout tool are also covered in this chapter.

Design example

In this chapter, you will create a full adder design in OrCAD Capture. The full adder design covered in this tutorial is a complex hierarchical design that has two hierarchical blocks referring to the same half adder design.

Duration:

40 minutes

Creating a design in Capture

Guidelines

When creating a new circuit design in OrCAD Capture, it is recommended that you follow the guidelines listed below.

  1. Avoid spaces in pathnames and filenames. This is necessary to get your design into downstream products, such as OrCAD PCB Editor or OrCAD PCB Router.
  2. Avoid using special characters for naming nets, nodes, projects, or libraries.
    While naming nets, use of the following illegal characters might cause the netlister to fail:
    • leading and trailing white spaces
    • ! (exclamation mark)
    • ' (single-quote)

Creating a project

To create a new project, we will use Capture's Project Wizard. The Project Wizard provides you with the framework for creating any kind of project.

  1. Launch Capture.
  2. From the File menu, choose New – Project.
  3. In the New Project dialog box, specify the project name as FullAdd.
  4. To specify the project type, select PSpice Analog or Mixed A/D.
    An Analog or Mixed A/D project can easily be simulated using PSpice. It also ensures that your design flows smoothly into the PCB layout tool for your board design.
  5. Specify the location where you want the project files to be created and click OK.
    The Create PSpice Project dialog box appears.
  6. In the Create PSpice Project dialog box, select Create a blank project.
    When you create a blank project, the project can be simulated in PSpice, but libraries are not configured by default. When you base your project on an existing project, the new project has same configured libraries.
  7. Click OK to create the FullAdd project with the above specifications.

    In case you already have a schematic design file (.dsn) that you want to simulate using PSpice, you need to create an Analog or Mixed A/D project using the File – New – Project command and then add your design to it.

The FullAdd project is created. In the project manager window, a design file, fulladd.dsn, is created. Below the design file, a schematic folder with the name SCHEMATIC1 is created. This folder has a schematic page named PAGE1.

Renaming the schematic folder and the schematic page

You will now modify the design to change the name of both the schematic folder and the schematic page, to HALFADD.

  1. In the project manager window, right-click SCHEMATIC1.
    You might need to expand fulladd.dsn to see SCHEMATIC1.
  2. From the pop-up menu, select Rename.
  3. In the Rename Schematic dialog box, specify the name as HALFADD.
  4. Similarly, right-click PAGE1 and from the pop-up menu select Rename.
  5. In the Rename Page dialog box, specify the page name as HALFADD and click OK.

After renaming of the schematic folder and the schematic page, the directory structure in the project manager window should be to similar to the following figure.

Using a design template

Before you start with the design creation process in OrCAD Capture, you can specify the default characteristics of your project using the design template. A design template can be used to specify default fonts, page size, title block, grid references and so on. To set up a design template in OrCAD Capture, use the Design Template dialog box.

  • To open the Design Template dialog box, from the Options drop-down menu choose Design Template.

To know more about setting up the design template, see OrCAD Capture User Guide.

Creating a flat design

In this section, we will create a simple flat half adder design with X and Y as inputs and SUM and CARRY as outputs.

Adding parts

To add parts to your design:

  1. Choose Place Part.
  2. In the Place Part dialog box, first select the library from which the part is to be added and then instantiate the part on the schematic page.
    The gates shown in Figure 2-1 are available in the 7400.OLB.

    Expand and use the Search for Part section in the Place Part dialog box, to search the library to which the required part belongs.
    To add 7400.OLB to the project, click the Add Library button ().

  3. Browse to <installation_directory>/tools/capture/library/pspice/7400.olb.
    Select 7400.OLB and click Open. Alternatively, you can double-click 7400.OLB.
    The 7400 library appears in the Libraries list box.
  4. Browse to <installation_directory>/tools/capture/library/pspice/eval.olb.
    Select EVAL.OLB and click Open.
    The 7400 and EVAL libraries appear in the Libraries list.

  5. Select 7400 in the Libraries list.
  6. Select 7408 (AND gate) from Part List.
    Note the PSpice symbol () and the layout symbol () that appear below the Packaging box. This denotes that the selected part can be simulated using PSpice and is enabled for the PCB Editor flow.
  7. Click the Place Part button (
    ) or click Enter.
    The part symbol is attached to the pointer.
  8. Click the schematic page to place the part.
  9. Place three instances of the AND gate, 7408, on the schematic page as shown in the following figure.

  10. Right-click and select End Mode.
  11. Similarly, place an OR gate (7432) and two NOT gates (7404) as shown in the following figure.

Connecting parts

After placing the required parts on the schematic page, you need to connect the parts.

  1. From the Place menu, choose Wire.
    The pointer changes to a crosshair.
  2. Draw the wire from the output of the AND gate, U2A, to the one of the inputs of the OR gate, U1B. To start drawing the wire, click the connection point of the output pin, pin3, on the AND gate.
  3. Drag the cursor to input pin, pin4, of the OR gate (7432) and click the pin to end the wire.
    Clicking on any valid connection point ends a wire.
  4. Similarly, add wires to the design until all parts are connected as shown in the following figure.

  5. To stop wiring, right-click and select End Wire. The pointer changes to the default arrow.

Adding ports

To add input and output ports to the design, complete the following sequence of steps:

  1. From the Place menu in Capture, select Hierarchical Port.
    The Place Hierarchical Port dialog box appears.
    Alternatively, you can select the Place port button from the Tool Palette.
  2. Add a library, CAPSYM.
  3. From the Libraries list box, select CAPSYM.
  4. First add input ports. From the Symbols list, select PORTRIGHT-R and click OK.
  5. Place two instances of the port as shown in the following figure.
  6. Right-click and select End Mode.
  7. To rename the ports to indicate input signals X and Y, double-click the port name.
    Avoid double-clicking the port symbol, as it displays Property Editor instead of Display Properties dialog box.
  8. In the Display Properties dialog box, change the value of the Name property to X and click OK.
    You can also use the Property Editor to edit the property values of a component. To know the details, see OrCAD Capture User Guide.
  9. Similarly, change the name of the second port to Y.
    You cannot use the Place Part dialog box for placing ports, because ports in CAPSYM.OLB are only symbols and not parts. Only parts are listed in the Place Part dialog box.
  10. Add two output ports. To do this, select PORTLEFT-L from the CAPSYM library.
  11. Rename the ports to SUM (connected to the OR gate) and CARRY (connected to the AND gate), respectively.

  12. Save the design.

The half adder design is ready. The next step is to create a full adder design that will use the half adder design.

Creating a hierarchical design

In Capture, you can create hierarchical designs using one of the following methods:

Another method of creating a hierarchical design is to create parts or symbols for the designs at the lowest level, and save the symbols in a user-defined library. You can later add the user-defined library in your projects and use these symbols in the schematic. For example, you can create a part for the half adder design and then instead of hierarchical blocks, use this part in the schematic. To know more about this approach, see Generating parts for a schematic.

In this section, we will create the full adder hierarchical design. The half adder design created in the Creating a flat design section will be used as the lowest level design.

Bottom-up method

When you create a hierarchical design using the bottom-up methodology, you need to follow these steps.

  • Create the lowest-level design.
  • Create higher-level designs that instantiate the lower-level designs in the form of hierarchical blocks.

In this section, we will create a full adder design using bottom-up methodology. The steps involved are:

  1. Creating a project in Capture. To view the steps, see Creating a project.
  2. Creating the lowest-level design. In the full adder design example, the lowest-level design is the half adder design. To go through the steps for creating the half adder design, see Creating a flat design.
  3. Creating the higher-level design. Create a schematic for the full adder design that uses the half adder design created in the previous step. To go through the steps, see Creating the full adder design.

Creating the full adder design

  1. In the project manager window, right-click fulladd.dsn and select New Schematic.
  2. In the New Schematic dialog box, specify the name of the new schematic folder as FULLADD and click OK.
    In the project manager window, the FULLADD folder appears below fulladd.dsn.
  3. Save the design.
  4. To make the full adder circuit as the root design (high-level design), right-click FULLADD and from the pop-up menu select Make Root.
    The FULLADD folder moves up and a forward slash appears in the folder.
  5. Right-click FULLADD and select New Page.
  6. In the New Page in Schematic: ‘FULLADD’ dialog box, specify the page name as FULLADD and click OK.
    A new page, FULLADD, gets added below the schematic folder FULLADD.
  7. Double-click the FULLADD page to open it for editing.
  8. From the Place menu, choose Hierarchical Block.
  9. In the Place Hierarchical Block dialog box, specify the reference as HALFADD_A1.
  10. Specify the Implementation Type as Schematic View.
  11. Specify the Implementation name as HALFADD and click OK.
    The cursor changes to a crosshair.
    For more information on Primitive option as well as on Path and Filename options in the Hierarchical Block dialog box, see OrCAD Capture User Guide.
  12. Draw a rectangle on the schematic page.
    A hierarchical block with input and output ports is drawn on the page.
  13. If required, resize the block. Also, reposition the input and output ports on the block.
    To verify if the hierarchical block is correct, right-click the block and select Descend Hierarchy. The half adder design you created earlier should appear.
  14. Place another instance of the hierarchical block on the schematic page.
    1. Select the hierarchical block.
    2. From the Edit menu, choose Copy.
    3. From the Edit menu, choose Paste.
    4. Place the instance of the block at the desired location.
      Alternatively, you can use the <CTRL>+<C> and <CTRL>+<V> keys to copy-paste the block.
  15. By default, the reference designator for the second hierarchical block is HALFADD_A2. Double-click the reference designator, and change the reference value to HALFADD_B1.
  16. Using the Place Part dialog box, add an OR gate (7432) to the schematic. (See Figure 2-2.)
  17. To connect the blocks, add wires to the circuit. From the Place menu, choose Wire.
  18. Draw wires from all four ports on each of the hierarchical blocks.
  19. Add wires until all the connections are made as shown in the following figure.
  20. Add stimulus to the design. In the Place Part dialog box, use the Add Library button to add SOURCSTM.OLB to the design.
    This library is located at <installation_directory>/tools/capture/library/pspice.
  21. From the Part List, select DigStim1 and click Place Part.
    The symbol gets attached to the cursor.
  22. Place the symbol at three input ports: port X of the HALFADD_A1, port X and Y of HALFADD_B1.
  23. Right-click the schematic and select End Mode.
  24. Specify the value of the Implementation property as Carry, X, and Y, respectively. See Figure 2-2.
  25. Add an output port, CARRY_OUT, to the output of the OR gate. (See Figure 2-2.)
    1. Select Place – Hierarchical Port.
      The Place Hierarchical Port dialog box opens.
    2. From the list of libraries, select CAPSYM.
    3. From the list of symbols, select PORTLEFT-L and click OK.
    4. Place the output port as shown in the Figure 2-2.
    5. Double-click the port name and change the port to CARRY_OUT.
  26. Save the design.

We have only added digital components to the design so far. We will now add a bipolar junction transistor to the SUM port of the HALFADD_A1 block.

  1. Select the Place Part tool button.
  2. In the Place Part dialog box, click the Add Library button.
  3. Select ANALOG.OLB and BIPOLAR.OLB and click Open.
  4. Select ANALOG.OLB and from the part list, add resistor, R. Place this resistor on the schematic and connect one end of the resistor to the SUM port of HALFADD_A1. See Figure 2-3.
  5. From BIPOLAR.OLB, select Q2N2222 and place it on the schematic. See Figure 2-3.
  6. Complete the circuit by adding a collector resistance, collector voltage, and ground. See Figure 2-3.
    Adding Collector Voltage
    1. To add the voltage, add the SOURCE.OLB library to the project.
    2. From the Part List, select VDC and click Place Part.
    3. Place the voltage source on the schematic. See Figure 2-3.
    4. By default, the source is of 0 volts. Using the Property Editor, change it to a voltage source of 5V. To do this, double-click the voltage source.
    5. In the Property Editor window, change the value of the DC parameter to 5.
    6. Save and close the Property Editor window.

    Adding Ground

    1. To add ground, select Place – Ground.
    2. From the part list, select 0 and click OK.
    3. Place the ground symbol on the schematic. See Figure 2-3.
  7. Add a connector, CON2 to the circuit. To do this, add a Capture library, CONNECTOR.OLB to the project.
    CONNECTOR.OLB is located at <installation_directory>/tools/capture/library .

You have successfully created the full adder hierarchical design using the bottom-up methodology. As the components used in this design are from the PSpice library, you can simulate this design using PSpice.

Top-down method

When you create a hierarchical design using the top-down methodology, use the following sequence of steps:

  • Create the top-level design using functional blocks, the inputs and outputs of which are known.
  • Create a schematic design for the functional block used in the top-level design.

This section provides an overview of the steps to be followed for creating a full adder using top-down methodology.

  1. Create a FullAdd project.
    To view the steps, see Creating a project.
  2. Create the top-level design, using the following steps:
    1. From the Place menu, choose Hierarchical Block.
      Alternatively, you can select the Place hierarchical block button from the Tool Palette.
  3. Draw the lowest-level design using the steps listed below. For the full adder design example, the lowest-level design is a half adder circuit.
    1. To draw the half adder design, right-click any one of the HALFADD hierarchical block.
    2. From the pop-up menu, select Descend Hierarchy.
    3. The New Page in Schematic: ‘HALFADD’ dialog box appears.
      Specify the page name as HALFADD and click OK.

    A new schematic pages appears with two input ports, X and Y, and two output ports, SUM and CARRY.


    You can now draw the half adder circuit on this schematic page using the steps covered in the Creating a flat design. Also see Figure 2-1.
    In the project manager window, a new schematic folder HALFADD gets added below fulladd.dsn.

Generating parts for a schematic

Instead of creating a hierarchical block for the half adder design, you can generate a part for the half adder design and then reuse the part in any design as and when required.

In this section of the tutorial, we will generate a part for the half adder circuit that you created in the Creating a flat design section of this chapter.

To generate a part from a circuit, complete the following steps.

  1. In the project manager window, select the HALFADD folder.
  2. From the Tools menu, choose Generate Part.
  3. In the Generate Part dialog box, specify the location of the design file that contains the circuit for which the part is to be made.
    For this design example, specify the location of fulladd.dsn.
  4. In the Netlist/source file type drop-down list box, specify the source type as Capture Schematic/Design.
  5. In the Part Name text box, specify the name of the part that is to be created, as HALFADD.
  6. Specify the name and the location of the library that will contain this new part being created. For the current design example, specify the library name as fulladd.olb.
  7. If you want the source schematic to be saved along with the new part, select the Copy schematic to library check box. For this design, select the check box.
  8. Ensure that the Create new part option is selected.
  9. To specify the schematic folder that contains the design for which the part is to be made, select HALFADD from the Source Schematic name drop-down list box.
  10. Click OK to generate the HALFADD part.
    The Split Part Section Input Spreadsheet dialog box opens.
  11. Click Save.

A new library, fulladd.olb, is generated and is visible under the Outputs folder in the project manager window. The new library also gets added in the Place Part dialog box. You can now use the Place Part dialog box to add the half adder part in any design.

Navigating through a hierarchical design

To navigate to the lower levels of the hierarchy, right-click a hierarchical block and choose Descend Hierarchy.

Similarly, to move up the hierarchy, right-click and select Ascend Hierarchy.

The Ascend Hierarchy and Descend Hierarchy menu options are also available in the View drop-down menu.

While working with hierarchical designs, you can make changes to the hierarchical blocks as well as to the designs at the lowest level.

To keep the various hierarchical levels updated with the changes, you can use the Synchronize options available in the View drop-down menu.

Select Synchronize Up when you have made changes in the lowest-level design and want these changes to be reflected higher up in the hierarchy.

Select Synchronize Across when you have made changes in a hierarchical block and want the changes to be reflected across all instances of the block.

Select Synchronize Down when you have made changes in a hierarchical block and want these changes to be reflected in the lowest-level design.

Processing a design

After you have created your schematic design, you may need to process your design by adding information for tasks such as, simulation, synthesis, and board layout. This section covers some of the tasks that you can perform in OrCAD Capture while processing your design.

Adding part references

To be able to take your schematic design to your PCB board layout tool for packaging, you need to ensure that all the components in the design are uniquely identified with part references. In OrCAD Capture you can assign references either manually or by using the Annotate command.

In the full adder design, annotation is not required at this stage because by default, unique part references are attached to all the components. This is so because by default, Capture adds part reference to all the components placed on the schematic page. If required, you can disable this feature by following the steps listed below.

  1. From the Options menu, choose Preferences.
  2. In the Preferences dialog box, select the Miscellaneous tab.
  3. In the Auto Reference section, clear the Automatically reference placed parts check box.
  4. Click OK to save these settings.

In case the components in your design do not have unique part references attached to them, you must run the Annotate command.

To assign unique part references to the components in the FULLADD design using the Annotate command, complete the following steps:

  1. In the project manager window, select the fulladd.dsn file.
  2. Choose Tools Annotate.
    Alternatively, you can click the Annotate button on the toolbar.
  3. In the Packaging tab of the Annotate dialog box, specify whether you want the complete design or only a part of the design to be updated. Select the Update entire design option.
  4. In the Actions section, do the following:
    1. Select the Incremental reference update option, if part references for all the parts are displayed as ?.
    2. Select the Unconditional reference update option, if part references are assigned for all the parts, but the part references assigned are not unique.
      To know about other available options, see the dialog box help.
  5. The full adder design is a complex hierarchical design. So select the Update Occurrences option in the Mode section.
    When you select the Update Occurrences option, you get a warning message. Ignore this message because for all complex hierarchical designs, the occurrence mode is the preferred mode. The Use Instances option is shown as preferred because the project type is Analog or Mixed A/D.
  6. For the rest of the options, accept default values and click OK to save your settings.
    The Undo Warning message appears.
  7. Click Yes.
    A message appears stating that the annotation will be done.
  8. Click OK.

Your design is annotated and saved. You can view the value of updated cross reference designators on the schematic page.


If you select the Annotate command after generating the board layout netlist, you will receive an error message stating that annotating at this stage may cause the board to go out of sync with the schematic design. This may cause further backannotation problems.

Creating a cross reference report

Using Capture, you can create cross reference reports for all the parts in your design. A cross reference report contains information, such as part name, part reference, and the library from which the part was selected.

To generate a cross reference report using Capture:

  1. In the project manager window, select the fulladd.dsn file.
  2. Choose Tools Cross Reference.
    Alternatively, you can choose the cross reference parts button from the toolbar.
  3. In the Cross Reference Parts dialog box, ensure that the Cross reference entire design option is selected.
    If you want to generate the cross reference report for a particular schematic folder, select the schematic folder before opening the Cross Reference Parts dialog box, and then select the cross reference selection option button.
  4. In the Mode section, select the Use occurrences option.
    Ignore the warning that is displayed when you select this mode. For complex hierarchical designs, you must always use the occurrence mode.
  5. Specify the report that you want to be generated.
  6. If you want the report to be displayed automatically, select View Output.
  7. Click OK to generate the report.

A sample output report is shown in the following figure.

Generating a bill of materials

After you have finalized your design, you can use Capture to generate a bill of materials (BOM). A bill of materials is a composite list of all the elements you need for your PCB design. Using Capture, you can generate a BOM report for electrical and as well as non-electrical parts, such as screws. A standard BOM report includes the item, quantity, part reference, and part value.

To generate a BOM report:

  1. In the project manager window, select fulladd.dsn.
  2. From the Tools menu, select Bill of Materials.
  3. To generate a BOM report for the complete design, ensure that the Process entire design option is selected.
  4. For a complex hierarchical designs, the preferred mode is the occurrence mode. Therefore, select the Use occurrences option.
    If you see a warning message stating that it is not the preferred mode, ignore the warning.
  5. Specify the name of the BOM report to be generated. For the current design, retain the default name, FULLADD.BOM.
    By default, the report is named as <designname>.BOM.
  6. Click OK.
    The BOM report is generated.

Getting your design ready for simulation

To be able to simulate your design using PSpice, you must have the connectivity information and the simulation settings for the analysis type to be done on the circuit design.

The simulation setting information is provided by a simulation profile (*.SIM). This section covers the steps to be followed in Capture for creating a simulation profile.

PSpice simulation require instance-level annotation present on parts. In case of reference designator related error, ensure to annotate the design in Instance mode before PSpice simulation.

For details about getting your design ready for simulation using PSpice, see Chapter 3, Preparing a design for simulation in the PSpice User Guide.

Creating a simulation profile from scratch

To create a new simulation profile to be used for transient analysis, complete the following steps:

  1. From the PSpice menu in Capture, choose New Simulation Profile.
  2. In the New Simulation dialog box, specify the name of the new simulation profile as TRAN.
  3. In the Inherit From drop-down list, ensure that none is selected and click Create.
    The Simulation Setting dialog box appears with the Analysis tab selected.
  4. In the Analysis Type drop-down list, Time Domain (Transient) is selected by default. Accept the default setting.
  5. Specify the options required for running a transient analysis. In the Run To Time text box, specify the time as 100u.
  6. Click OK to save your modifications and to close the dialog box.

You can now run transient analysis on the circuit. Note that the Simulation Setting dialog box also provides you with the options for running advanced analysis, such as Monte Carlo (Worst Case) analysis, Parametric analysis and Temperature analysis. You may choose to run these as and when required.

To know details about each option in the Simulation Settings dialog box, click the Help button in the dialog box.

Creating a simulation profile from an existing profile

You can create a new simulation profile from an existing simulation profile. This section covers the steps for creating a new simulation profile, SWEEP, from an existing simulation profile, named TRAN.

  1. From the PSpice menu, choose New Simulation Profile.
  2. In the New Simulation dialog box, specify the profile name as SWEEP.
  3. In the Inherit From drop-down list, select FULLADD-TRAN.
  4. Click the Create button.
    The Simulation Settings dialog box appears with the general settings inherited from the existing simulation profile. You can now modify the settings as required and run PSpice to simulate your circuit.

Adding Layout-specific properties

To be able to take your design to your PCB board layout tool for placement and routing, you need to add the footprint information for each of the components in your design.

By default, some footprint information is available with all the components from the PSpice-compatible libraries located at <installation_directory>\tools\capture\library\pspice. However, these footprints are not valid. You need to change these values to valid footprint values. You can add footprint information either at the schematic design stage in OrCAD Capture or during the board design stage in the PCB board layout tool. In this section, you will learn to add footprint information to the design components during the schematic design stage.

To add footprint information to the OR gate, 7432, in the FULLADD schematic page, complete the following steps.

  1. Right-click the OR gate and select Edit Properties.
    The Property Editor window appears.
  2. In the Filter by drop-down list, select Allegro PCB Designer.
  3. To change the value of the PCB Footprint property, click the corresponding cell and type in the value as SOIC14.
  4. Press ENTER or click Apply.
  5. Save the changes and close the Property Editor window.

Similarly, add PCB Footprint information for all the components in the design. The component name and the corresponding footprint information to be added is listed in the following table.

For PCB Editor:

Component...

PCB Footprint...

AND gate (7408)

SOIC14

OR gate (7432)

SOIC14

NOT gate(7404)

SOIC14

Resistance

RES500

Connector(CON2)

JUMPER2

Transistor(Q2N2222)

TO18

Your design is now ready to be taken to the PCB board layout tool for placement and routing.

Design rules check

After you have completed your design, it is recommended that you run design rules check (DRC) to isolate any unwanted design errors that might be there in the design.

To run DRC on the full adder design, complete the following steps:

  1. In the project manager window, select the design file, fulladd.dsn.
  2. From the Tools menu, select Design Rules Check.
    Alternatively, you can select the Design Rules Check button from the toolbar.
  3. In the Design Rules Check dialog box, the Design Rules Options tab is selected by default. Specify your preferences.
    By default, the Check entire design option is selected. To run DRC on the complete design, accept the default selection.
  4. Select the Use occurrences option in the Mode section.
    For complex hierarchical designs, the occurrence mode is the preferred mode. Therefore, ignore the warning that is displayed when you select the Use occurrences option.
  5. To run the DRC, select the Check design rules option in the Action section.
  6. In the Design Rules section, select the type of rules to run, that is electrical and/or physical rules.
    1. Use the Electrical Rules tab to define electrical rules to test. Also define the report information to be generated from the Reports section.
    2. Similarly, use the Physical Rules tab to define physical rules to test. Also define the report information to be generated from the Reports section.

    For the current design example, select Check unconnected bus nets (in the Electrical Rules tab) and Report identical part references (in the Physical Rules tab).

  7. Select the View Output check box.
    When this check box is selected, the DRC report is opened automatically for viewing after the checks are complete.
  8. In the Report File text box, specify the name and the location of the DRC file to be created.
    For the current design example, specify the filename as fulladd.drc.
  9. Click OK.

After the checks are done, the DRC report is displayed in the following format:

Summary

This chapter covered the steps for creating both flat and hierarchical designs using OrCAD Capture. In the process, you were introduced to basic design creation tasks, such as creating projects, adding libraries to a project, placing parts, and editing property values.

What’s next

In the next chapter, Simulating a design, you will use PSpice for simulating the schematic design created in this chapter. You will be introduced to various types of simulations and their need in the PCB design cycle.

Recommended reading

For more information about OrCAD Capture, see OrCAD Capture User Guide and Capture online help.

TOC




Simulating a design

This chapter consists of the following sections:

Objective

PSpice is a simulator provided by OrCAD and can be used to simulate both analog and digital circuits. PSpice simulator is closely integrated with OrCAD Capture to provide you with a rapid design-and-simulate iterative cycle. Using PSpice, you can explore various design configurations before committing to a specific implementation.

In this chapter, you will use PSpice to simulate the full adder design that you created in Chapter 2, Creating a schematic design using OrCAD Capture. In this chapter, you will also learn about the various types of analysis that can be performed using PSpice.

Simulation using PSpice

PSpice models the behavior of a circuit containing any mix of analog and digital devices.

To simulate a design, PSpice needs to know about the:

  • circuit topology
  • analysis type
  • simulation models that correspond to the parts in your circuit
  • stimulus definitions to test with

Files generated by PSpice

After reading various data files and any other required inputs, PSpice starts the simulation. As the simulation progresses, PSpice saves the simulation results in two files, the Waveform data file and the PSpice output file.

  • Waveform data file: The data file contains simulation results that can be displayed graphically. PSpice reads this file and displays waveforms reflecting circuit response at nets, pins, and parts that you marked in your schematic (cross-probing).
  • PSpice output file: This is a user-configurable file. Depending on the options specified by the user, this file may or may not contain any information. To configure the output file, you can use the Options tab in the Simulations Settings dialog box, as shown in the following figure.

For detailed description of the .OPTION command, see PSpice Reference Guide.

For more information on Files needed and generated by PSpice refer to PSpice User Guide, Chapter 1, Things You Need to Know.

Analysis types

You can perform the following types of circuit analysis using PSpice:

  • DC Analysis
  • AC Analysis
  • Transient Analysis
  • Advanced Analysis

DC analysis

DC Analysis includes the following:


DC Sweep analysis

The DC sweep analysis causes a DC sweep to be performed on the circuit that allows you to sweep a source (voltage or current), a global parameter, a model parameter, or the temperature through a range of values. The bias point of the circuit is calculated for each value of the sweep.

To run a DC sweep or small-signal DC transfer analysis, you need to place and connect one or more independent sources and then set the DC voltage or current level for each source.


Bias Point analysis

The bias point is calculated for any analysis whether or not the Bias Point analysis is enabled in the Simulation Settings dialog box.


DC Sensitivity analysis

DC sensitivity analysis calculates and reports the sensitivity of one node voltage to each device parameter for the following device types:

  • resistors
  • independent voltage and current sources
  • voltage and current-controlled switches
  • diodes
  • bipolar transistors

For more information on each type of DC analysis, refer to PSpice User Guide, Chapter 9, DC Analyses.

AC analysis

AC analysis includes the following:


AC Sweep analysis

AC sweep is a frequency response analysis. PSpice calculates the small-signal response of the circuit to a combination of inputs by transforming it around the bias point and treating it as a linear circuit.


Noise analysis

When running a noise analysis, PSpice calculates and reports the following for each frequency specified for the AC Sweep/Noise analysis:

  • Device noise is the noise contribution propagated to the specified output net from every resistor and semiconductor device in the circuit. For semiconductor devices, the device noise is also broken down into constituent noise contributions where applicable.
  • Total output and equivalent input noise

For more information on each type of AC analysis, refer to PSpice User Guide, Chapter 10, AC Analyses.

Transient analysis

A transient analysis calculates the behavior of the circuit over time.

For more information on transient analysis, refer to Chapter 12, Transient Analysis in the PSpice User Guide.

Besides the analysis types discussed above, you can use PSpice to perform some more analyses that help you evaluate and enhance the performance of your circuit. These analyses cannot be performed independently, but you can configure the simulation profile to run these analyses along with Transient, AC, or DC analysis. These are:


Parametric analysis

Parametric analysis performs multiple iterations of a specified standard analysis while varying a global parameter, model parameter, component value, or operational temperature. The effect is the same as running the circuit several times, once for each value of the swept variable.


Temperature analysis

For a temperature analysis, PSpice reruns standard analyses set in the Simulation Settings dialog box at different temperatures.

You can specify zero or more temperatures. If no temperature is specified, the circuit is run at 27°C. If more than one temperature is listed, the simulation runs once for each temperature in the list.

For more information on parametric and temperature analysis, see Chapter 11, Parametric and temperature analysis of PSpice User Guide.


Monte Carlo analysis

The Monte Carlo analysis calculates the circuit response to changes in part values by varying all of the model parameters for which a tolerance is specified. This provides statistical data on the impact of variance of a device parameter.


Worst Case analysis

Worst-case analysis is used to find the worst probable output of a circuit or system given the restricted variance of its parameters. For instance, if the values of R1, R2, and R3 can vary by +-5%, then the worst-case analysis attempts to find the combination of possible resistor values that result in the worst simulated output.

For more information on Statistical analysis, refer to PSpice User Guide, Chapter 13, Monte Carlo and Sensitivity/Worst case Analysis.

Overview of the full adder design

In this chapter, we will simulate the full adder design using PSpice. The full adder design is a complex hierarchical design that has two hierarchical blocks referring to the same half adder design.

To go through the steps detailed in this chapter, you should have the full adder design ready. You can either create the full adder design or use the one provided to you along with the tutorial.

For more information on creating the full adder design, see Chapter 2, “Creating a schematic design,”.

To copy the design files provided with the tutorial, unzip the flowtut.zip file shipped along with the tutorial. This file is located at <installation_directory>/doc/flowtut/tutorial_example. The partial directory contains files generated at the end of Chapter 2, “Creating a schematic design.” Use the files in this directory only if you want to skip the design creation steps covered in Chapter 2 and directly move on to Chapter 3.

Simulating the full adder design

To provide PSpice with information about the type of simulation you wish to perform and the resources to be used in your simulation, you must create a simulation profile before you can start a PSpice simulation. A simulation profile saves your simulation settings for an analysis type so that you can reuse them easily.

In this section, we will use the TRAN.sim profile to perform transient analysis on the full adder circuit.

For more information on creating the TRAN.sim profile, see Getting your design ready for simulation.


Whether you create the full adder design, or use the one from the design files provided with the tutorial, ensure that the design is annotated ( Tools – Annotate) in the instance mode ( Update Instances) before you run PSpice Simulation.

Editing a simulation profile

After you have created a simulation profile, you can still make modifications to it. We will edit the TRAN.sim profile to configure a stimulus file for providing inputs to X, Y and Carry.

  1. In the project manager window, right-click FULLADD-TRAN simulation profile.
    Expand Simulation Profiles under PSpice Resources in the project manager to view the FULLADD-TRAN node.
  2. From the pop-up menu, select Edit Simulation Settings.
  3. In the Simulation Setting dialog box, select the Configuration Files tab.
  4. From the Category list box, select Stimulus.
  5. In the Filename text box, specify the location of the stimulus file.
    To use the stimulus file provided with the sample file, extract the sample files from flowtut.zip and specify the location of FullAdd-PSpiceFiles\input.stl.
  6. Select the Add to Design button.
  7. Click OK to save the settings.

Running PSpice

  • To simulate the design, choose PSpice – Run.

The PSpice Netlist Generation progress box appears indicating that the PSpice netlist is being generated.

During netlisting, a warning stating that the PSpiceTemplate property is not found on instance J1 is generated. You can ignore this property because component J1 is required for board layout and is not required for simulation purposes.

After the netlist generation is complete, the design is simulated and PSpice is started. The Output window in PSpice indicates that the simulation is complete.

Though the simulation is complete, the Probe window does not yet display any waveform that might help you analyze the circuit behavior and determine the validity of your design.

Viewing Output Waveforms

After simulating a design using PSpice, you can plot the output waveforms in the Probe window. This will help you visualize the circuit behavior and determine the validity of your design. You can analyze the output waveforms and evaluate your circuit for performance analysis and data comparison from multiple files.

Using the Probe window, you can:

  • view simulation results in multiple Probe windows
  • compare simulation results from multiple circuit designs in a single Probe window
  • display simple voltages, currents, and noise data
  • display complex arithmetic expressions that use the basic measurements
  • display Fourier transforms of voltages and currents, or of arithmetic expressions involving voltages and currents
  • for mixed analog/digital simulations, display analog and digital waveforms simultaneously with a common time base
  • add text labels and other annotation symbols for clarification

For PSpice to display output waveforms in the Probe window, you need to perform at least one of the following steps.

Place markers

You place markers in your circuit design in Capture to indicate the points where you want to see simulation waveforms displayed in PSpice.

You can place markers:

  • before simulation to limit results written to the waveform data file, and automatically display those traces in the active Probe window.
  • during or after simulation, to automatically display traces in the active Probe window.

You can control the trace display for any of parameter by using the Data Collection tab. For example, if the None option is selected, PSpice will not display any waveform at the point where a marker is placed.

To add markers, choose PSpice – Markers.

To view the markers in the simulation results, the schematic must be open.

You can also use the buttons provided on the PSpice toolbar to add markers.

We will now modify the full adder design in Capture by adding Voltage markers to view the output waveforms in the Probe window.

  1. Choose PSpice – Markers – Voltage Level.
    Alternatively, you can click the Voltage/Level Marker button on the toolbar.
  2. Place the marker between transistor Q1 and resistor R1, as shown in the following figure.

  3. To view the output waveform at the marker location, double-click the marker.
    The output waveform appears in the Probe window in PSpice. See Figure 3-1.

If you add markers before simulating the design, the output waveforms are displayed automatically in the Probe window after the simulation is complete.

Add Plot Window template

In addition to markers, you can place Plot Window Template markers in Capture. A Plot Window Template marker will restore the associated template when you run the simulation in PSpice.

The analysis type defined in the profile will determine the type of template that will be loaded.

To place a plot window template marker, select Markers from the PSpice menu, and then select Plot Window Templates.

Add complex traces

By default, the waveforms that PSpice displays are the simple voltages, currents, and noise data from your circuit. Using the Trace menu in PSpice, you can add traces that are complex arithmetic expressions that use the basic measurements, such as Fourier transforms of voltages and currents and arithmetic expressions involving voltages and currents.

Configuring the Probe window

Using the Plot menu in PSpice, you can control the settings for the X- and Y-axis in the Probe windows. Using the Plot menu, you can also customize the grid settings in the Probe window and add text labels and other annotation symbols to your traces. You can also configure the way you want to view the waveforms by defining display settings on the Probe Window tab in the Simulation Settings dialog box.

Performing parametric analysis

In this section, you will perform the Parametric Sweep analysis on the full adder design. You will evaluate the influence of varying base resistance on the switching characteristics of the transistor.

To do this, you need to perform the following steps:

  1. Modify the full adder circuit by changing the value of resistor R2 to a variable {RES}. For more information, see Changing the value of R2 to the expression {RES}.
  2. Place a PARAM part to declare values of the parameter {RES}. For more information, see Adding a PARAM part to the FULLADD design.
  3. Create a new simulation profile or modify the existing profile to set up the parametric analysis.

In this example, there will be multiple simulation runs, one for each value of resistor R2. After the analysis is complete, you can analyze output waveforms for the analysis runs using PSpice A/D.

Adding a variable circuit parameter

Changing the value of R2 to the expression {RES}

  1. Open the full adder design, FullAdd.opj, in OrCAD Capture.
  2. To display the Property Editor window for R2, double-click resistor R2.
  3. In the Value text box, replace the original value of 10K with {RES}.
  4. Click Apply to save the modifications.

Curly braces indicate that the variable or the expression within the braces will evaluate to a numerical value.

Adding a PARAM part to the FULLADD design

  1. From the Place menu in Capture, choose Part.
  2. Using the Place Part dialog box, add SPECIAL.OLB to the FULLADD project.
    SPECIAL.OLB is in the directory <installation_directory>\tools\capture\library\pspice.
  3. In the Libraries list box, select SPECIAL.OLB.
  4. From the Part List list box, select PARAM and click the Place Part icon.
  5. Place an instance of the PARAM part on the schematic page.
  6. Double-click the PARAM part to display the Property Editor and click New Property.
    The Add New Property dialog box appears.
    In the Property Editor window, you can also display properties names as column headings. In such cases, to add a new property, click the New Property button. The Add New Property dialog box will appear.
  7. In the Name text box, enter RES, without curly braces.
  8. Specify the value as 10K and click OK.
    The Display Properties dialog box appears.
  9. In the Display Format section, select Name and Value and click OK.
  10. Click Yes in the undo warning message that appears.
    This creates a new property for the PARAM part, as shown by the new property labeled RES in the Property Editor window.
  11. Click Apply to update all the changes to the PARAM part.
  12. Close the Property Editor window.

You can view the changes on the schematic page.

For more information about using the Property Editor, see the OrCAD Capture User Guide.

Adding a Plot Window Template marker

In this section, we will add a Plot Window Template marker to the circuit and observe the change in the output for different values of R2.

  1. Remove the voltage marker added to the schematic design in the Place markers section.
  2. From the PSpice menu in Capture, choose Markers and then select Plot Window Template.
  3. Select the Risetime of Step Response template marker from the Plot Window Templates dialog box and click Place.
  4. Place the marker between transistor Q1 and resistor R1, as shown in the following figure.

Setting up parametric analysis

In this section, we will use the FULLADD-SWEEP simulation profile to set up the parametric analysis. This simulation profile has been created by inheriting the settings from the FULLADD-TRANS profile. See Creating a simulation profile from an existing profile.

The simulation profile created in the Creating a simulation profile from an existing profile section, does not cover the settings for the parametric analysis. Therefore, we need to modify the FULLADD-SWEEP simulation profile. To do this, you first make SWEEP the active simulation profile in Capture and then open the profile for modifications.

  1. In Capture, select FULLADD-SWEEP from the Active Profile drop-down list box.
  2. From the PSpice menu, choose Edit Simulation Profile.
    The Analysis tab of the Simulation Settings dialog box appears.
  3. Select the Parametric Sweep check box in the Options list box.
  4. Select the Global parameter option under Sweep Variable. This sets the value to the sweep value and all expressions are re-evaluated.
  5. Type RES in the Parameter name text box.
  6. Type 25K, 50K, and 5K in the Start value, End value, and Increment text boxes, respectively.
  7. Click OK.

Instead of creating a new profile in OrCAD Capture, you can create a new simulation profile in PSpice also by inheriting settings from an existing profile. The new profile will work with your circuit design and can also be modified within PSpice. To modify a simulation profile in Capture, you use the Edit Simulation Profile command from the PSpice menu. In PSpice, use the Edit Settings command from the Simulation menu.

Running the simulation

To run the Parametric analysis, choose Run from the PSpice menu.

When the simulation is complete, the Simulation complete message appears in the output window, and the Available Sections dialog box appears as shown in the following figure.

This dialog box appears for all multi-run analyses.

Select the runs for which you want to display the data and click OK. This loads the simulation results window.

To read more about Parametric Analysis, see the Parametric analysis section in Chapter 11, Parametric and temperature analysis of the PSpice User Guide.

You can use the Performance Analysis Wizard to create a Performance Analysis trace for evaluating the performance of your circuit. To know more about the Performance Analysis wizard, see Chapter 11, Parametric and temperature analysis of the PSpice User Guide.

Exporting output waveforms

You can export the output waveforms in the following formats:

  • .dat file
  • .stl file
  • .txt file
  • .csv file

To export the output waveform:

  • From the File menu in PSpice, select Export and then select the desired format.

Summary

This chapter covered the steps for simulating the full adder design using OrCAD PSpice. In this chapter, you were introduced to various tasks involved in the simulation process, such as placing markers and templates, modifying a simulation profile, and analyzing simulation results.

What’s next

In the next chapter, Board design using OrCAD PCB Editor, you will use OrCAD PCB Editor to create a PCB board for the full adder design.

Recommended reading

For more information about PSpice, see PSpice User Guide and PSpice online help.

TOC





Board design using OrCAD PCB Editor

This chapter consists of the following sections:

Overview

The OrCAD PCB Editor (based on the Allegro® PCB technology) place-and-route tool offers PCB designers the power and flexibility to create and share PCB data and constraints across the design flow. It is a interactive environment for creating and editing complex, multilayer PCBs. The feature set provided by OrCAD PCB Editor addresses a wide range of today’s design and manufacturability challenges.

Objective

In this chapter, you will use OrCAD PCB Editor to take the full adder design created in Chapter 2, Creating a schematic design, to a PCB board. This chapter details some of the common tasks involved in PCB Editor. In the process, you will also use cross-probing between Capture and PCB Editor.

Tutorial design

To go through the steps detailed in this chapter, you should have the full adder design ready. The full adder design used in this tutorial is a hierarchical design. It has two instances of the HALFADD hierarchical block.

You can either use the design you created in Chapter 2, Creating a schematic design or if you want to skip the design creation section, you can pick up the design files shipped with the tutorial.

Installing design example

The design files for the full adder design are available in the flowtut.zip file shipped along with the tutorial. The flowtut.zip is located at <installation_directory>/doc/flowtut/tutorial_example.

Unzip the flowtut.zip file and extract it to an empty directory, say orcad_flow. On extracting the flowtut.zip file, you will find two sub-directories, partial and complete, created in the orcad_flow directory.

The partial directory contains files generated at the end of Chapter 2, “Creating a schematic design.” Use the files in this directory only if you want to skip the design creation steps covered in Chapter 2 and directly move on to Chapter 4.

The complete directory contains all the files generated through all the chapters in this tutorial. You can use the files in the complete directory to verify your results.

Estimated completion time

30 minutes

Preparations in Capture

To be able to take a design created in Capture to PCB Editor, you need to complete some tasks. Some of these tasks are performed in Capture while the rest are completed in the PCB Editor environment.

The tasks that are to be completed in Capture are:

Running DRC

Before taking a design from a schematic editor to a board planner, it is recommended to run design rules check (DRC). This step is performed in Capture. To view the procedure, see Design rules check.

Creating PCB Editor netlist

After running the design rule checks, you create the PCB Editor netlist in Capture.

  1. In the project manager window, select the design file, fulladd.dsn.
  2. From the Tools menu in Capture, select Create Netlist.

    The Create Netlist dialog box appears.

  3. Select the PCB tab (if not already selected).
    The Create PCB Editor Netlist check box is selected by default. Selecting this check box generates a netlist in PCB Editor format, which consists of the following three files:
    • PSTCHIP.DAT: This file contains a description for each different type of part used in the design.
    • PSTXNET.DAT: This connectivity file, also referred to as the flat list or expanded net list, contains each net, its properties, its attached nodes, and node properties.
    • PSTXPRT.DAT: This file, also referred to as the expanded parts list, contains a list of physical parts and lists each reference designator and the sections assigned to it, ordered by reference designator and section number.

      Ensure that the correct configuration file (allegro.cfg) is specified in the Setup dialog box. To view the configuration file, click Setup. The configuration file path should be <installation_directory>\tools\capture\allegro.cfg.
      The Netlist Files Directory text box contains the directory location where the PST*.DAT files will be saved. The default location is an allegro subdirectory in your design directory.
  4. Select the View Output check box to automatically open the three PST*.DAT netlist files in separate Capture windows for viewing and editing after netlisting is completed.
  5. Select the Create or Update PCB Editor Board (Netrev) check box to create the PCB Editor board that corresponds to the netlist you are generating.
    The Output Board File text box contains the board name, which in this case is fulladd.brd and the directory location where the board file will be created, which in this case is \allegro.
  6. Select the Open Board in OrCAD PCB Editor option to open the Output Board File in OrCAD PCB Editor automatically after the netlisting is completed.
  7. Click OK in the Create Netlist dialog box.
    A message appears asking you to save your design prior to creating the netlist.

    Click OK.

    Capture generates the netlist files (PSTCHIP.DAT, PSTXPRT.DAT, and PSTXNET.DAT) and the board file (fulladd.brd) in the specified directory location, which in this case is \complete\allegro. Also, the netlist files are opened in separate Capture windows and they appear under the Outputs directory in the project manager window as shown in the following figure.

    A board file, fulladd.brd, opens in OrCAD PCB Editor.

Creating a board

Having created the PCB Editor netlist, the next step is to create a new board in PCB Editor. The Capture netlister generates the board file and three PCB Editor-compatible netlist files. See Creating PCB Editor netlist for more information.

Creating a board outline

The board outline defines the boundary of the board. To create a board outline in PCB Editor:

  1. From the Add menu, select Line. The Options panel changes as shown in the following figure.

    Ensure the Options panel on the right hand side of the PCB Editor window displays Active Class as Board Geometry and Subclass as Outline.

  2. Specify the following settings in the Options window:
    1. Line lock: Line, 90
    2. Line width: 20.0
    3. Line font: Solid
      The default user units in PCB Editor is mils. To view the user units, choose Design Parameters from the Setup menu. In the Design Parameter Editor dialog box, click the Design tab. The User units is defined in the Size section.

    In the Display tab, click the Setup grids button. In the Define Grid dialog box, you can see that the grid size spacing for X and Y coordinates in PCB Editor is 25 mils each.

  3. To insert the first corner of the board outline, place the cursor at the coordinates: 1000, 3000 and click the left-mouse button.
    As you move the cursor in the design window the coordinates will keep changing. You can view the coordinates at the bottom right hand corner of the PCB Editor window.

    You can also use the pick command in PCB Editor console to specify the coordinates. For example, to specify the starting point, enter pick 1000 3000.
  4. Complete the remaining board outline using the following coordinates:
    • 3000, 3000
    • 3000, 5000
    • 1000, 5000
  5. When you are at the last corner of the board outline, right-click and select Done. The board outline is created.
    Ensure the board outline is a closed polygon. For this tutorial, the closed polygon is square in shape.
  6. Select Display – Zoom – Fit to display the entire board outline in the design window as shown in the following figure.

    Alternatively, you can use any one of these methods to fit your board outline in the design window:

    • Type zoom fit at the command line prompt.
    • Press F2.
    • Click the icon.

Adding mounting holes

After the board outline is created, let us now add mounting holes in the board.


To add mounting holes in your board

  1. From the Place menu, select Components Manually. The Placement dialog box appears.
  2. Select the Advanced Settings tab.
  3. Select the Library check box under the List construction section.

  4. Click OK to close the Placement dialog box.
  5. Select Manually from the Place menu again.
  6. In the Placement dialog box, select the Mechanical symbols option from the drop-down menu.
  7. Select the desired mechanical symbol. For this tutorial, select the mechanical symbol, MTG125.

  8. Click Hide.
  9. The Placement dialog box closes and the mechanical symbol, MTG125 attaches to the cursor.
  10. Move the mechanical symbol to the top-left corner of the design window and left-click to release the symbol.
  11. Right-click and select Done. The mechanical symbol is placed.
  12. Repeat steps 5 to 11 to place the mechanical symbols on the remaining three corners of the design window.


    Alternatively, select Copy from the Edit menu and left-click the mechanical symbol placed on the design window. The selected mechanical symbol attaches to the cursor. Move the symbol to the desired location in the design window and left-click to release the symbol. Now, right-click and select Done.

Placing components

After you have created the board outline, you can start placing your components in the board. OrCAD PCB Editor supports both manual placements and auto placements.

In this section, we will use manual placements to create the PCB board for the full adder design. There are different ways in which you can select a component for placement. In this tutorial, you will learn to place components by refdes only.


Selecting components by refdes

  1. From the Place menu, select Components Manually. The Placement dialog box appears showing in a collapsing tree view all the components that you can place in your design. For example, for this tutorial the components are: J1, Q1, R1, R2, U1, U2, U3, and U4
    Only unplaced components are displayed in the Placement dialog box.
  2. Select the U1 component by clicking the check box next to the component name as shown in the following figure.


    You can also select all the components of a type by clicking the check box next to the folder icon.
    The Quickview section displays the footprint shape for the selected component in graphics and text mode.
  3. Click Hide. The Placement dialog box closes and the component name(s), in this case, U1 that you have chosen attaches to the cursor.
  4. Move the component to the desired location and right-click and select Rotate from the pop-up menu.
    Make sure that a rotation angle is defined in the Options panel. For this tutorial, the rotation angle is 90.
  5. Rotate the component in anti-clockwise direction and left-click to release the component.
  6. Repeat steps 2 to 5 until all the components available in the Placement dialog box are placed in the design window as shown in the following figure.

  7. Select Refresh from the View menu to refresh your screen.

    To find a component in PCB Editor:
    • In the Find panel of the PCB Editor window.
    • Select the Symbol (or Pin) option from the Find By Name drop-down list.
    • Click More. The Find by Name or Property dialog box appears displaying all the available components.
    • Select a component that you want to find. The selected component appears in the Selected objects grid.
    • Click OK. The component is highlighted in the design window.

Similarly, you can find net(s) or symbol(s) in PCB Editor. To find a net, select the Net option from the Find By Name drop-down list.

Design rules check

PCB Editor allows you to run DRC online ( On) or in batch mode ( Off). The default is On. While placing the components, if there are any design rule violations, then error markers are displayed on the board.

To run DRC online, select Setup – More – Enable On-Line DRC. To verify the basic spacing and physical constraints for your board design, select Setup – Constraints – Spacing. A window appears showing the default settings. For this tutorial, we will accept the default values.

Routing

After completing the board placement, you can route the full adder board to complete the electrical connections between components. OrCAD PCB Editor supports both manual routing and Autorouting. The general use model is to first route the critical nets manually, lock them and then autoroute the rest of the board.

Manual routing

The steps involved in the manual routing process are as follows:

  • Check the board outline, via definitions, routing and via grids
  • Route power and ground
  • Fan out surface mounted devices and verify connections to power and ground
  • Route the remaining signals using the manual routing tools
  • Optimize routing using the manual routing commands
  • Check for route spacing violations and check routing statistics

To know more about each of these steps, see PCB Editor documentation.


Manually routing VCC and GND nets

Before you start routing the VCC and GND nets, make sure that you delete the NO_RAT property attached to these nets. To delete this property:

  1. Select Object Properties from the Edit menu.
  2. In the Find panel, select the Net option (if not already selected) from the Find By Name drop-down list.
  3. Enter VCC and click More. The Edit Property dialog box appears displaying all the properties attached to the VCC net.
  4. Select the NO_RAT property in the Available Properties list box. The property definition appears in the panel on the right-hand side of the dialog box. For information about PCB Editor properties, see PCB Editor documentation.

  5. Select the Delete check box adjacent to the No_Rat property name.
  6. Make the Value drop-down menu empty.
  7. Click Apply.
  8. Click OK to close the Edit Property dialog box.

You can use the Edit Property dialog box to add or delete properties from a component or net.

To manually route the VCC and GND nets:

  1. Select the Find tab in the right hand side of the PCB Editor window. The Find panel is displayed.
  2. Select the Net option from the Find By Name drop-down list.
  3. Click More. The Find by Name or Property dialog box appears displaying all the available nets.
  4. Select VCC. The VCC item appears in the Selected objects grid.
  5. Click OK. All VCC nets are highlighted in the design window.
  6. Select Connect from the Route menu.
    Alternatively, you can press F3 or click the icon.
  7. Change Line width to 20.00 in the Options panel.
  8. Now, click the net to be routed.
  9. Draw the net through the desired path.
  10. When you have completed routing, right-click the net and select Done.
    Similarly, perform the above steps for manually routing the GND nets.


Manually routing remaining nets

To manually route remaining nets:

  1. Press F2 to fit your board in the design window.
  2. Place the cursor on the net to be routed and press F11 to zoom in.
  3. Select Connect from the Route menu or Press F3. The Options pane changes.
  4. Click the net to be routed. The Options pane changes as shown in the following figure.


    Make sure the Line lock settings are Line, 45.
  5. Draw the net through the desired path.
  6. When you have completed routing, right-click the net and select Done.

To change layers while routing (adding Vias):

  1. Click the net to be routed.
  2. Right-click the net and select Add Via. A Via is added. The currently Active layer becomes the Alternate layer and the Alternate layer become the Active Layer and vice-versa. For example, if you have a Top and a Bottom layer, where TOP is current Active Layer, then when you add Via, the Bottom layer will become the Active layer and the Top layer becomes the Alternate layer.
  3. Draw the net through the desired path.
  4. When you have completed routing, right-click the net and select Done.

For this tutorial, the routed board will appear as shown in the following figure. A sample routed board, fulladd.brd is available at: /complete/allegro.

Autorouting using PCB Editor

OrCAD PCB Editor supports autorouting of board, components, and DRC.

Board autorouting implies that the nets on the complete board are routed. Component routing routes only the nets attached to the selected component.


To autoroute a board

  1. Choose Route PCB Router Route Automatic. The Automatic Router dialog box appears.
  2. Click Route. The board is routed.
    For more information, see PCB Editor documentation.

Autorouting using OrCAD PCB Router

When you select the OrCAD PCB Router auto router, the complete board is routed. PCB Router uses shape-based routing and is a faster routing tool.

To use the PCB Router auto router:

  1. From the Start menu, select PCB Router.
  2. Specify the design file to be loaded.
    The PCB Router ShapeBased Automation Software dialog box appears displaying the design file.
  3. Select Route from the AutoRoute menu. The AutoRoute dialog box appears.
  4. Select the Basic option in the AutoRoute dialog box. For more information, see the PCB Router documentation.
  5. To start autorouting, click OK.
    The autorouting process starts and the board is routed.

Post-processing

This section introduces some of the tasks that are not a part of the placement and routing process, but are related and can be performed using OrCAD PCB Editor.

To know more about post-processing, see the PCB Editor documentation.

Renaming components manually

After you have completed the placement and routing of your PCB board, you can rename the components manually on the PCB board in a specific order.

  1. From the Edit menu, select Text.
  2. Left-click the reference designator you want to modify. The selected reference designator appears in the command line.
  3. Change the reference designator as desired in the command line and press the Enter key.
    PCB Editor renames the components. The reference designators for the component on the board changes.
  4. Save the board file and close PCB Editor.

Automatic renaming of components

  1. Select Manufacture – Auto Rename Refdes – Rename. The Rename Refdes dialog box appears.
  2. Select the Use default grid option button. This option uses the default grid, which constitutes an internal method of renaming components.

  3. Click Setup. The Rename Ref Des Set Up dialog box appears on which you set all the reference designator parameters. For more information, see the PCB Editor documentation.
  4. Accept the default settings (for this tutorial) and click Close in the Rename Ref Des Set Up dialog box.
    The Rename RefDes dialog box appears again.
  5. Click Rename.
    PCB Editor automatically renames every component on your design in a single operation. The status of the renaming operation is displayed in the command line.

Back annotation

While creating a PCB board, you might make some changes in the PCB Editor board (.brd) file. As a result, the board file and the design file in Capture may be out of sync. To ensure that both these file are in sync, you can backannotate the changes in the PCB board file to the Capture.

When you backannotate, information, such as component location and component names (changed due to renaming) gets added on to the schematic in Capture.

To backannotate the changes to the schematic:

  1. Open FullAdd.opj in Capture.
  2. In the project manager window, select fulladd.dsn.
  3. Choose Tools Back Annotate. The Backannotate dialog box appears.
  4. Select the PCB Editor tab, if not selected.
  5. Select the Generate Feedback Files option button (if not already selected).
    Make sure that the correct configuration file (allegro.cfg) is specified in the Setup dialog box. To view the configuration file, click Setup. The configuration file path should be <installation_directory>\tools\capture\allegro.cfg.
    Make sure the Netlist Directory text box contains the directory location where the updated netlist files (PST*.DAT) will be saved. The default location is an allegro subdirectory in your design directory.
  6. Navigate to the directory location where the .SWP file needs to be saved. A .SWP file is generated by Capture after you make changes to your board file (.BRD). To know more about the .SWP file, see OrCAD Capture User Guide. For this tutorial, the .SWP file name is fulladd.swp and the directory where the file will be saved is: /complete/allegro.
  7. Select the Update Schematic check box (if not already selected), if you want the Capture schematic design (fulladd.dsn) to be updated with back annotation information from the .SWP file.
  8. Select the View Output (.SWP) File check box to automatically open the .SWP file in a separate Capture window for viewing and editing after the .SWP file is generated. This check box is not selected by default.

  9. Click OK in the Backannotate dialog box. A message appears asking you to save your modified design prior to creating a new netlist file and a .SWP file.
  10. Click Yes.

Capture generates the netlist files (PSTCHIP.DAT, PSTXPRT.DAT, andPSTXNET.DAT) and creates the fulladd.swp file in the specified directory location, which in this case is \complete\allegro. The .SWP file is opened in a separate Capture window and also appears under the Outputs directory in the Project Manager window.

The schematic is updated with the changes in the board file based on the generated .SWP file.

Similarly, if the board file is open in PCB Editor and you make changes in the schematic design, you can ensure that these changes are forwarded to the board during netlist creation in Capture.

To do this:

  1. In the project manager window, select fulladd.dsn.
  2. From the Tools menu, choose Create Netlist.
  3. In the PCB Editor tab of the Create Netlist dialog box, specify the base board directory location. For this tutorial, the base board directory is /complete/allegro/fulladd.brd.
  4. In the Output Board File text box specify the board name and the directory location where the updated board file will be created.
  5. Click OK in the Create Netlist dialog box.
    Capture generates the netlist files (PSTCHIP.DAT, PSTXPRT.DAT, and PSTXNET.DAT) and the updated board file is created in the specified directory location. The changes in the schematic design will appear in the board file.

Cross probing and cross highlighting between PCB Editor and Capture

OrCAD PCB Editor is tightly integrated with OrCAD Capture. As a result, you can use cross-probing to verify information flow between the schematic design and the board design and conversely.

Cross-probing lets you select an object in the Capture schematic and see the corresponding object in PCB Editor.

To enable cross-probing, you must enable intertool communication between Capture and PCB Editor. To do this:

  1. In the project manager window in Capture, select fulladd.dsn.
  2. From the Options menu in Capture, choose Preferences.
  3. Click the Miscellaneous tab.
  4. Ensure that the Enable Intertool Communication check box is selected in the Intertool Communication section.
  5. Click OK.

Before you start cross probing, tile the Capture and PCB Editor windows. Select a component in Capture. PCB Editor automatically displays the corresponding components.

For example, if you select R1 in the FULLADD.DSN file, the corresponding resistor R1 will be displayed in PCB Editor as shown in the following figure.

Cross highlighting lets you select an object in PCB Editor and see the corresponding object highlighted in Capture.

In case of cross highlighting between PCB Editor and Capture, first select Highlight from the Display menu, then select a component in PCB Editor the corresponding component is highlighted in Capture.

For example, if you select R1 in the FULLADD.BRD file, the corresponding resistor R1 will be highlighted in Capture.

If you want to turn off highlighting, select Dehighlight from the Display menu.

Generating output

The final task in creating a board design is to generate output files. You can create Gerber files, drill files, DXF files, and printer/plotter files.

Before you generate reports and output files, you should take a backup of your design and clean up the design. To clean up your design:

  1. Select Route Gloss – Parameters. The Glossing Controller dialog box appears.
  2. Click Line Smoothing. The Line Smoothing dialog box appears.
  3. Accept the default settings and click OK.
  4. In the Glossing Controller dialog box, click Gloss.

The design is cleaned up. You can now generate the desired output files and reports.


Before creating a output file (artwork), make sure you run DRC Update from the Check menu in PCB Editor.

Output files

Using PCB Editor, you can generate various files that can further be used with various third-party tools, such as GerbTool, VisualCAD, AutoCAD, and so on.

To generate these output files, complete the following steps:

  1. Select Export Gerber Parameters.
    The Artwork Control Form dialog box appears.

  2. Select the Gerber RS274X option button under the Device type section.
  3. Accept the default settings and click OK to close the Artwork Control Form dialog box.
  4. Again select Export Gerber Parameters.
  5. Select the Film Control tab.
  6. Select the check boxes corresponding to the film layer(s). For this tutorial, both the TOP and BOTTOM layers are selected.

  7. Click Create Artwork. A message appears showing the progress of the artwork creation. After the artwork is created the artwork files with a.ART extension are saved under \complete\allegro design directory (for this tutorial only).
  8. Click OK to close the Artwork Control Form dialog box.

You can view the artwork files that you created in PCB Editor.


Only Cadence® artwork is supported.

To view the artwork:

  1. Select Import – More – Artwork. The Load Cadence Artwork dialog box appears.
  2. Browse the name of the artwork file (.ART) that you want to load in the Filename text box.
  3. Select a subclass from the Subclass drop-down menu.

  4. Click Load File. A dynamic rectangle that represents the extents of the Gerber data appears in the UI work area.
  5. Left-click the dynamic rectangle to place the artwork on the design window. The artwork is placed on the design window.

To toggle between the TOP and BOTTOM artworks, select the Visibility tab and choose the artwork you want to view from the Views drop-down list. The chosen artwork is displayed in the design window.

Reports

You can create a variety of reports using PCB Editor.

To create reports, complete the following steps:

  1. From the Export menu, select Quick Reports.
  2. Select the reports you want generated. For the full adder design, select the Component Report option.

Summary

In this chapter, you were introduced to OrCAD PCB Editor, which is a place-and-route tool provided by OrCAD. You completed the tasks required to take a design from OrCAD Capture, a schematic design tool, to a place and route tool. You were also introduced to OrCAD PCB Router, which is also a tool used to place-and-route the printed circuit boards.

What’s next

This is the last chapter in the OrCAD Flow Tutorial. In the Glossary, you will find the definitions of various terms used in this tutorial.

Recommended reading

For more information about OrCAD PCB Editor, see PCB Editor documentation.


PCB Editor documentation

PCB Editor documentation includes:

  • Allegro® PCB Editor User Guide
  • Allegro PCB and Package Physical Layout Command Reference Table of Contents
  • Allegro Platform Properties Reference

To learn about OrCAD PCB Router, see the PCB Router User Guide.

TOC




Glossary


autorouting

Automatic routing performed by a computer application based on a set of rules called strategies.


Bill of Material

A bill of materials is a composite list of all the elements you need for your PCB design


board geometry

The physical definitions of the design’s base material.


bottom-up methodology

A design methodology in which you first create lowest level design and then create hierarchical blocks for these lowest-level designs.


boundary

A line that defines the outside edge of a window.


circuit

A set of electronic functions, such as gates and buffers, that when connected together constitute the electronic description of a printed circuit design.


class

A category used to identify and refer to elements in a design. It eliminates the requirement of referring to elements by layer number.


command line

The line, identified in the console window by the > prompt, at which the user can enter commands.


Complex hierarchy

A design in which two or more hierarchical blocks (or parts with attached schematic folders) reference the same schematic folder.


cross probing

When intertool communication is enabled in Capture, selecting objects in Capture causes the corresponding objects to be highlighted in the layout tool. Also, selecting objects in the layout causes the corresponding objects to be highlighted in Capture. Both applications must be open.


cross reference report

A cross reference report contains information such as part name, part reference, and the library from which the part was chosen.


design

For OrCAD PCB Editor: a database file with a .brd file name extension. A design drawing usually contains two outer ETCH subclasses (TOP and BOTTOM), internal ETCH subclasses, padstacks, vias, edge connectors, and components.


design rule

A guideline that specifies any of a number of parameters for the printed circuit board. These may include minimum clearance between items that belong to different nets, or connection rules. Also, these rules may include specifications for track width to carry a given current, maximum length for clock lines, termination requirements for signals with fast rise and fall times, and so on.


Design Rules Check (DRC)

Design Rules Check (DRC) is executed to isolate any unwanted design errors that might exist in the design


design template

Is used to specify the default characteristics of your project, such as default fonts, page size, title block, and grid references


DO file

A .DO file is a text file that contains a sequence of autorouter commands. The order of commands in a do file is very important because the autorouter executes each command in sequence.


ETCH

A routing class.


ETCH subclass

A routing layer. For example, TOP or BOTTOM.


flat design

A schematic design that has no hierarchical blocks or port and has no parts with attached schematic folders. A flat design can have multiple schematic pages such that the output lines of one schematic page connect laterally to input lines of another schematic page using off-page connectors. Flat designs are practical for small designs with few schematic pages.


glossing

Applications that perform post-processing functions including increasing the width of connections to ensure greater manufacturing reliability, converting corners to arcs, and adding dieelecric patches to hybrid designs to insulate intersecting connection.


Hierarchical design

A design in which schematic folders are interconnected vertically with hierarchical blocks. At least one schematic folder, the root schematic folder, contains symbols representing other schematic folders.


layer

An insulated plane in the design that contains lines of etch.


mechanical symbol

A set of information contained in a file having a .bsm filename extension used to define mechanical and graphic elements on a design drawing. Typically, design symbols represent non-electrical elements, for example, design outlines, plating bars, mounting holes, or card ejectors.


multi-run analysis

Result in a series of DC sweep, AC sweep, or transient analysis depending on the basic analysis that you enabled.


net

Any set of pins and vias that are logically connected.


netlist

An ASCII text file that provides the electrical blueprint for the circuit design.


ratsnest

Unrouted connection between two pins on a PCB board.


reports

User-defined files that provide specific information about a design.


Simple hierarchy

A design in which there is a one-to-one correspondence between hierarchical block (or parts with attached schematic folders) and the schematic pages they reference. Each hierarchical block (or part with attached schematic folder) represents a unique schematic page.


subclass

(For OrCAD PCB Editor)

Further defines a class. You can define subclasses for a class.


surface mount

A component mounting technology in which holes are not required.


TOP

An ETCH subclass. One of the outer layers.


Technology template

A file that contains a board outline and the appropriate design rules, drawing formats, dimensions for spacing and grids, preplaced components, and tooling holes for a specific type of board.


Top-down methodology

A design methodology in which you first create top-level design using the hierarchical blocks and then create schematic designs for the hierarchical blocks.


track

Routed connection between two pins on a PCB board

TOC