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OrCAD PCB Flow Tutorial

OrCAD Front-to-Back Design Flow Tutorial



Allegro® Design Entry HDL and OrCAD PCB EditorAllegro® PCB Editor can be used for a seamless front- to-back flow while designing your printed circuit board (PCB). The tight integration between the tools, and the existence of utilities that allow you to create and update libraries and perform manufacturing tasks, provide a comprehensive solution for your design tasks.

This tutorial shows you how to create and edit library parts and schematics, package a design, and generate a routed board ready for manufacturing.


Note: The commands and steps described in this document may not be accessible depending on the licenses and product options available or selected. Refer to Cadence Online Support ( or the Cadence site ( for more information.


Download: RAK database and references can be found at ‘Attachments’ and ‘Related Solutions’ sections below the PDF. This RAK pdf can be searched with the document title on

PCB Flow


In the Cadence PCB flow, Design Entry HDL is used to capture the logic of a PCB in schematic form. The design is then packaged and imported to PCB Editor to place, route, and generate the manufacturing output for fabrication of PCB. The schematic and the board files can be synchronized throughout the flow. Various library management tools, such as Part Developer, Pad Designer, and Symbol Editor, can be used to create parts and update libraries.




DDR3 Design Example


The design example in this tutorial has a DDR3 controller packaged inside a Ball Grid Array (BGA), with the necessary voltage supervisors, and connectors for Power Input and DIMM Connector to plug in the DDR Memory ICs.


Note: The DDR3 design was developed internally at Cadence.


The following figures show the design hierarchy in the Hierarchy Viewer and the schematic design for page1.



The schematic project, the board file, and the libraries are available in the examples folder shipped with this tutorial. Extract the content of the archive in your system to view, customize, or use the design files

Brief Outline of Chapters


The PCB Flow Tutorial is divided into three chapters:


Preparing Schematic and Board Library



The tasks covered in this chapter include creating a schematic part symbol and footprint of a part by referring to a downloaded datasheet. The tools used are:

  • Part Developer
  • Pad Designer
  • Symbol Editor

Creating Schematic Designs

  • This chapter lists the tasks to open a project, add libraries, and define project paths, search and add components, connect parts, name wires, add ports, create and tap busses, and package the design. The tool used is Allegro Design Entry HDL.


Working with Board

  • This chapter lists the tasks to import a netlist, create a board outline, define a cross section, define constraints, place parts, route the board using Autorouter, gloss the board after routing, perform delay tuning, and prepare artwork. The tool used is Allegro PCB Editor.



To know more about the tools mentioned in this chapter, refer to:

  • Allegro Design Entry HDL Tutorial
  • Allegro Design Entry HDL User Guide
  • Allegro PCB and Package Physical Layout Command References
  • Allegro User Guide
  • Defining and Developing Libraries User Guide
  • Part Developer User Guide
  • Part Developer Tutorial


Preparing Schematic and Board Library                   


To create a design or a board, you need to ensure the schematic symbols and PCB parts you are going to use are available in your libraries. Although the schematic editors and board layout tools have their own libraries and your organization will have a repository of part libraries, you might need to create or customize some of the parts you are going to use in your design.


Cadence library creation and management tools such as Part Developer, Pad Designer, and Symbol Editor, can be used to create symbols, padstacks, and footprints.


In this chapter, you will create a footprint and schematic symbol for LTC3618, which is a synchronous step-down regulator. You will use Pad Designer and Layout Editor to create the footprint. After creating the footprint, you will create a schematic symbol using Part Developer.


Creating Footprints


To create a footprint, perform the following tasks:

  1. Create padstacks
  2. Define package outline and place padstacks


In this section, you will create a padstack and define package outline using information from the downloaded datasheet for LTC3618. The Package Description section of the datasheet is of interest to you while creating the footprint.


Creating Padstacks

You will create a single-layer, surface mount padstack, with a regular pad, a soldermask pad, and a pastemask pad for assembly process.


Before creating the padstack, consult the datasheet to determine the dimensions.

As can be seen in the figure, the dimension of each pad in millimeters is 1.05 by 0.45. The soldermask pad should be bigger than the regular pad. Therefore, you can specify it to be 1.40 by 0.80 millimeters.


To create the padstack, perform the following steps:

1. Start Pad Designer by doing one of the following:

  - Enter the command <installation_directory>\tools\pcb\bin\pad_designer
  - From the Start menu of Windows, choose Cadence — Release 16.6 —PCB Editor Utilities — Pad Designer.

2. In the Parameters tab, set Units to Millimeter and Decimal places to 2.
3. In the Layers tab, ensure that Single layer mode is selected.
5. In the Regular Pad group, set Geometry to Rectangle, Width to 1.05, and Height to 0.45.
6. Specify Regular Pads for SOLDERMASK_TOP with the following settings:
     Geometry: Rectangle

7. Width: 1.4
8. Height: 0.80
9. Specify Regular Pads for PASTEMASK_TOP with the following settings:
    Geometry: Rectangle

10. Width: 1.05
11. Height: 0.45
12. Save the padstack as smd42_18 (File — Save As).


Defining Package Outlines and Placing Padstacks


The Package Symbol Wizard provides an easy way to create a package symbol. The wizard is designed to help beginning users create a simple package symbol and to enable experienced designers to create a base package symbol that they can modify into a more complex symbol.



Referring to the Package Description section of the datasheet, you can determine the following variables required to create a package symbol:

  • Number of pins (N): The package has 25 pins, out of which one pin is on the top of the package. You will create the 24 pins on the two sides using the Package Symbol Wizard. You will place the top pin manually.
  • Lead pitch (e): The lead pitch is 0.65 mm.
  • Terminal row spacing (e1): The terminal row spacing derived from the datasheet is
  • 7.65mm.
  • Package width (E): The package width is derived as 4.55mm.
  • Package length (D): The package length is derived as 7.88mm.


Using Package Symbol Wizard


1. Start the Package Symbol wizard and specify the name as TSSOP25.
     To start the Package Symbol wizard:
      a. Start PCB Editor: Either use the command allegro or, in Windows, from the Start menu choose Cadence — Release 16.6 — PCB Editor.
      b. Choose File — New and then select Package symbol (wizard).

2. Select SOIC as Package Type.

3. Click Next.

4. Click Load Template and then click Next.

5. Specify Units used to enter dimension in this wizard as Millimeter and set the Accuracy to 2.

6. Click Next.

7. Specify the following parameters:



8. Click Next.
9. Specify smd42_18 as the default padstack.
10. Click Next.
11. Ensure that Center of symbol body is selected. This will make placing the manual pin easier.
12. Ensure that Create a compiled symbol is selected.
13. Click Next.
14. Click Finish.


Placing a Manual Pin

You will place a manual pin on top of the symbol


1. Choose Layout — Pins.

2. In the Options pane, ensure that Connect is selected.
3. Specify the Padstack as smd128_108.
4. Set the X Spacing and Y Spacing as 1.27.
5. Set Rotation to 90.
6. Specify Pin # as 25.
7. Ensure that Offset for X and Y are 0.
8.  Click on top of the symbol to place the pin at the center.



9. Save the DRA


This will save the DRA file and generate a package symbol file (PSM), in this example TSSOP25.psm.


Creating Schematic Parts


To create a schematic part, you will need to refer to the Pin Configuration and Pin Functions sections of the datasheet.


Do the following to create a schematic part:

  1. Create a new cell
  2. Create a package
  3. Add logical pins
  4. Add physical pins
  5. Map logical and physical pins
  6. Generate symbol

Each of the listed tasks is explained in the following sections.


Creating a New Cell

  1. Start Project Manager.
  2. To start Project Manager: Use the command projmgr or, in Windows, from the Start menu, choose Cadence — Release 16.6 — Project Manager.
  3. Open the required project.
  4. Click the Part Developer button.
  5. In Part Developer, choose File — New — Cell.
  6. Select mylib from the Library list.
  7. Specify the Cell as LTC3618.
  8. Click OK.


Creating a Package


To create the package, perform the following steps:

  1. Right-click Packages in the cell tree and choose New.
  2. In the Logical & Physical Parts tree, right-click Physical Parts (Pack Types) and choose New.
  3. In the add Physical Part dialog box, enter TSSOP and click OK.


Adding Logical Pins


To enter the logical pins, perform the following steps:

  1. Click the Package Pin tab.
  2. Choose Pins — Add.
  3. Add the pins after referring to the datasheet.


Adding Physical Pins


You will specify a footprint and extract the physical pins from the footprint.


To specify JEDEC_TYPE, perform the following steps:

  1. Click the General tab.
  2. Open Browse Jedec Type by clicking the browse button next to the Jedec Type field.
  3. Select TSSOP25 and click OK.

To extract the physical pins, perform the following steps:

  1. Click Package Pin tab.
  2. Select Footprint — Extract from Footprint.
  3. Click Yes.


Mapping Pins

To map a logical pin to a physical pin, in the Package Pin tab, select the logical pin row and then select the physical pin. Click Map.


Generating Symbol

To generate the symbol, in the Package Pin tab, click Generate Symbol(s). Click OK when the Generate Symbol(s) for Package LTC3618 dialog box appears.


References for Schematic and Board Library

To know more about the topics discussed in this chapter, refer to:

  • Defining and Developing Libraries User Guide
  • Allegro Command References
  • Part Developer User Guide
  • Part Developer Tutorial


Creating Schematic Designs


After creating the parts and libraries, you will create a schematic using Allegro® Design Entry HDL (DE HDL). DE-HDL is the tool used for design capture in the PCB design flow.


With DE-HDL, you can create a project, place components (parts), connect parts, name signals, add ports, and save designs. You can also run various utilities, such as Rules Checker, Archiver, Crefer, and Bill of Materials (BOM). When you save a design, DE- HDL checks for errors. From these errors, you can locate the areas on the schematic where connectivity errors have occurred.


Design Entry HDL supports the following two use models: pre-select and post-select. The post-select model is the default use model. You can modify the use model if required from the General page of the Tools dialog box. The instructions in this document are for the post-select model of DE-HDL.


Creating Projects

To create a project, do the following:


  1. Open Project Manager.
  2. Choose File – New – New Design.
  3. Enter a name for the design project, say ddr3, browse to the directory where you want to create your design project, and click Next.
  4. To add a library to the Project Libraries list, select the required library from the Available Libraries list and click Add.
  5. Click Next in the New Project Wizard – Project Libraries dialog.
  6. Enter a name for the design, say ddr3, in the Design Name field and click Next. A summary of the choices you made for the project is displayed.
  7. Click Finish.
  8. The project is created and a status message is displayed. Click OK.



Setting up Projects

To set up the project, do the following:


1. Click Setup in the Project Manager dialog to set up the project.
2. If you want to include any libraries in your project, you can add them in cds.lib. To modify cds.lib, click the Edit button. The cds.lib file opens in a text editor.
3. Add the following statement to the cds.lib file for the project:
     - DEFINE libraryname librarypath
     - INCLUDE <location of the cds.lib file to be included>
     - Where libraryname is the logical name for the directory specified in librarypath.
     - The libraryname is the name that appears in the list of Available Libraries in Project Setup.



      DEFINE ddr3_lib worklib


      INCLUDE D:\Cadence\SPB_16.6\share\cdssetup\cds.lib




      DEFINE custom D:\DesignProject\libs


4. Save the cds.lib file and close it. Click Yes in the message box that appears. In the Project Setup dialog, a custom-named library is added to the Available Libraries list.
5. Click on the Add button.
6. You can use the Up or Down buttons in the Project Libraries list to define the position of the library.



To learn more about creating and setting up new DE-HDL projects, see the Project Manager User Guide.


Opening Different Tools


When DE-HDL is launched, it reads the project and library definition files in the project directory. These files determine which design to open and the libraries to access, and the setup options that the tool should use.


You can customize these project settings using the Tools tab in the Project Setup dialog. For example, you can set up PCB footprints from PCB Editor Setup, or define the default text editor that you want to use to open files. After defining setup options as required, click Apply then OK. For details, see the Setting up Tools section in Allegro® Design Entry HDL User Guide.


Creating Logical Designs

After clicking the OK button in the Project Setup dialog, you will return to the Project Manager dialog.

  1. Click the Design Entry button.
  2. To create the schematic, first add page borders. To add page borders, choose Component – Add.
  3. Select any page border from the standard library. For the current design, you will select B size page from the standard library.


Searching and Adding Components to Schematic

  1. To search for and add components to the schematic, choose Component – Add or right-click on the schematic page and select Add Component.
  2. In Component Browser, select a library, say Custom, from the Browse Libraries list and select a component, say ltc3618, from the Cells list.
  3. In the box at the bottom of Component Browser, select a row. The selected part is displayed in a separate tab in Component Browser. If there are multiple symbols for the selected component, you can choose any symbol you want to place on the schematic based on your requirements.
  4. Click the Add button then minimize or close the Component Browser dialog to place the component on the schematic.
  5. After placing the component on the schematic, right-click on the schematic and select Done or use the Esc key.
  6. Similarly, place other components. For example, place TXB0108RGYR from the same custom library on the schematic.


Connecting Parts


To connect parts using wires or nets, do the following:

  1. Choose Wire – Draw.
  2. Click the pins you want to connect. For example, click the B1 pin of TXB0108RGYR then click RUN1 of the LCT3618EFE#PBF component. Similarly, connect the other pins as illustrated in the following snapshot.




Naming Wires


In this section, you will specify user-defined names for connectivity across components.


  1. Choose Wire – Signal Name.
  2. Type one or more signal names on separate lines (say, NET1, NET2, NET3, NET4, and NET5).
  3. Select the wires you are naming in the same order in which you entered the names in the Signal Name dialog box.



Note: Voltage symbols in DE-HDL contain an HDL_POWER property. The global signal names used by the netlister are identified by this property. When you save your schematic, DE-HDL checks that all voltage symbols have the VOLTAGE property; you can disable this, if required, in the Tools — Options menu.


Adding Ports

Port signals are used to label interface nets on a block in a hierarchical design. You can use port signals to connect components across pages in the hierarchical design, for placement of cross-referenced signals, and to navigate the design.


To add ports, do the following:


  1. Open Component Browser from Component – Add.
  2. From the standard library, select INPORT and click the Add button.
  3. Connect the INPORT with a wire to a pin. For example, the A1 pin of TXB0108RGYR (I5).



Creating and Tapping Buses


A vectored signal indicates many bits on the wire. Special connection symbols—bus taps—must be used to tap bits from a vectored signal. To create and tap a bus, choose Wire – Draw and add a wire as illustrated by the red arrow in the following image.



Naming Buses


Design Entry HDL supports several bit numbering syntax conventions. Since the signal name syntax affects library parts and many design tools, a single site must use the same syntax system wide.


To name the bus you drew in the previous section, do the following:


  1. Choose Wire – Signal Name.
  2. Enter the signal name in the dialog box; for example, enter following signal name in the dialog box that appears: PP_DQ<8..0>.
  3. Click on the bus wire to attach its corresponding signal name. The wire automatically thickens to differentiate it from regular, single-bit wires.



Adding Bus Taps


1. Choose Wire — Bus tap.


2. Click to add a connection between the component’s pin; for example, VDDQN and PP_DQ<8..0>.

3. Similarly, add other bus taps. For example, in the following figure a total of eight bus taps are added. Finally, right-click and select Done.


Assigning Bit Numbers to Bus Taps


Zoom into the schematic so that the part you need to work with is clearly visible, then do the following:


  1. Choose Wire – Bus Tap Values.
  2. Set the MSB and LSB values. For example, set MSB value to 7 and LSB to 0 and click Apply.
  3. Click to start the guideline near the bottommost bus tap and click again near the topmost bus tap to stop the guideline as illustrated in the following figure.



This assigns the bits in the proper order, as shown in the following figure Error! Reference source not found.


Saving the Design


When you save a schematic, the information is saved in the sch_1 directory. Choose File — Save All


This command saves all sheets that have been opened and edited, but not saved during the DE-HDL session.


Note: DE-HDL runs various checks, such as electrical checks, graphic checks, and name checks, before saving the schematic design. You can change the default settings from Tools – Options – Check. You can also run the Rules Checker tool to apply various checks after you package the design (Export Physical). For information on Design Entry HDL Rules Checker, see Allegro Design Entry HDL Rules Checker User Guide.



Netlisting and Design Annotation

After you complete the design, you will package the design to automatically generate part reference designators ($LOCATION property), and packaging files (pst *.dat files). The packaging results are stored in the packaged view. This view includes the backannotation report, netlist, state, error and marker files. 

  1. To package the design, choose File – Export Physical in Design Entry HDL.
  2. Select radio buttons and check boxes based on your requirement, say the Preserve, Update PCB Editor Board (netrev), and BackAnnotate Packaging Properties to Schematic Canvas options. You can browse to the required directories for the input and output board files.
  3. After selecting the appropriate check boxes, click OK.


Note: You can customize packaging options by clicking the Advanced button. For details, see the Packager-XL Reference guide.

After packaging the design, depending on your requirements, you can run Cross Referencer (Crefer), BOM, and Variant Editor. You can also plot your design.



  • To learn how to use the Design Entry HDL utilities—CRefer, Archiver and BOM— see Design Entry HDL Utilities User Guide.
  • For information on the Design Variance solution (design variants), see Design Variance User Guide and Design Variance Tutorial.
  • To learn how to plot a design, see the Plotting Your Design chapter of Allegro Design Entry HDL User Guide.



Working with Board


After creating the schematic and packaging the design in Allegro® Design Entry HDL, prepare the board for manufacturing in Allegro® PCB Editor. This chapter describes the tasks you will perform in PCB Editor to place and route the components and then to prepare the board for manufacturing.


Importing Netlist

To import the netlist, perform the following steps:


1. Set the Cadence tab of the Import Logic dialog box (File — Import — Logic) as shown in the following figure.


2. Note that the Import directory should be set to the packaged directory where you exported the physical design from Design Entry HDL. This directory contains the pst*.dat files and is, by default, the current directory.

3. Click Import Cadence.


Creating Board Outline


You will create a 7000 MIL by 3000 MIL board with package and route keepin boundaries at a distance of 40 MIL from the board edge.


Set up the work area before creating the board outline. Defining the work area makes navigation easy. To set up the work area, perform the following steps:

  1. Choose Setup — Design Parameters to open the Design Parameter Editor window.
  2. Specify the Size and Extents. For example, in the DDR3 design, the User units is Mils and Size is D.

        -Note that D is the default size for Mils and Inch.



To create the board outline, perform the following steps:


  1. Choose Setup — Outline — Board Outlines.
  2. In the Board Outline dialog box, specify the Board Edge Clearance as 40.00 MIL. This defines the space between the board outline and the package and route keepin boundaries. The package and route keepin boundaries are automatically generated when you create a boundary outline.
  3. Click to mark the bottom-left and top-right locations of the outline. On the status bar note the coordinates of the points you click, and ensure that the board is 7000X4000 MIL. Note that in the Board Outline dialog box Edit is selected under Command Operations. A dotted outline is displayed in the canvas.
  4. Click OK. The board outline, as well as, the route and package keepin outlines are visible. You can view the class and subclass information in the Options pane by selecting an outline. You might need to change the visibility of the layers to view package and route keepin outline information because in normal view you will see only one of the two overlapping outlines.



To learn more about creating outlines, see:

  • The board outline section in the Allegro PCB and Physical Layout Command Reference: B Commands manual.


Defining Cross Section


In the Layout Cross Section dialog box (Setup — Cross-section) define the layer stack- up as shown in the following figure.



To add or delete a layer, right-click a subclass name and choose the appropriate option from the pop-up menu.

For example, to add the layer GND1 below the TOP layer, right-click and choose Add Layer Below.


To learn more about cross sections, see:

  • The Layout Cross Section Dialog Box section in the Allegro PCB and Physical Layout Command Reference: D Commands manual.


Defining Constraints


You can set all constraints from either the schematic editor or the board layout editor. When a design is exported from Design Entry HDL, the constraints are propagated to PCB Editor. Similarly, you can add constraints in the Constraint Manager and synchronize the constraints with the schematic.


You can create and assign different types of constraints; such as physical, electrical, and spacing. You can assign the defined constraints to various elements; such as clines, vias, shapes, pins, and so on.


This section describes how to create a physical constraint, setup a constraint region, and then implement the constraint region.


To define a physical constraint set (CSet):

1. In Constraint Manager, create a new physical CSet named RGN_CS using the Create Physical CSet dialog box (Objects — Create — Physical CSet).
2. In the Physical tab, select All Layers under Physical Constraint Set and define the constraint set as shown in the following figure.



Now you can assign the CSet to any elements, such as nets, by performing the following steps:

3. Select All Layers under Net in the Physical tab.
4. Select the Referenced Physical CSet cell for a net.
5. Select the CSet from the list.


To implement constraint region setup, do the following steps:

6.  In Constraint Manager, select All Layers under Region in the Physical tab.
7.  Right-click the DSN name in the Name column and choose Create — Region.
8.  Specify a name for the region, say, BGA.
9.   Right-click BGA and choose Create — Region-Class.
10. Select BGA and DIFF_NCLASS and click OK.


Similarly, you can add other region classes.

11. Apply physical constraints to each region; for example, RGN_CNS and DIFF are applied in the following figure.
12. Close Constraint Manager.


To implement the constraint region, perform the following in PCB Editor:


1. Choose Shape — Rectangular.
2. In the Options pane, specify the class as Constraint Region, the subclass as All and select Bga in the Assign to Region field, as shown in the following figure.

3. Draw the constraint region shape by windowing around the region where you want to implement the constraint region. For example, window around the BGA in the DDR3 design.



To learn more about constraint management, see:

  • Constraint Manager User Guide
  • Constraint Manager Command Reference
  • Allegro Design Entry HDL - Constraint Manager User Guide
  • Allegro Platform Constraints Reference
  • Allegro Platform Properties Reference
  • For "Constraint Region Process" refer ‘Related Articles’ sections below the PDF.  This RAK pdf can be searched with the document title on


Placing Parts

In PCB Editor, components can be placed both manually and automatically. In automatic placement, the layout editor places elements based on placement properties that restrict or influence component positioning and part packaging.


You may want to alternate manual placement with automatic placement. You can preplace sensitive or fixed parts manually, run automatic placement, and then rearrange some autoplaced parts. You could finish by optimizing the overall placement of a design with manual placement.


To place parts manually, perform the following steps:


  1. In the Placement List tab of the Placement dialog box (Place — Manually), select the listed components by checking Components by refdes.
  2. Click on the canvas to place the components. The next available component is automatically attached to the cursor when a component is placed.
  3. Click OK to close the dialog box when all components are placed.



To learn more about placing parts, see:


  • Allegro User Guide: Placing the Elements
  • Allegro PCB and Physical Layout Command Reference: P Commands



Routing the Board Using Autorouter

You can route a design automatically using the autorouter or perform a manual routing using the Add connect button  ).


Before routing ensure that route keepin is defined, all components are placed, and constraints are defined and set.


To perform routing using autorouter, perform the following steps:

  1. Ensure Entire design is selected in the Automatic Router dialog box (Route —PCB Router — Route Automatic).
  2. Click Route.




To learn more about routing, see:


  • Allegro User Guide: Routing the Design


Glossing the Board after Routing


The automatic glossing process eliminates vias and smoothens routed traces on the board to improve the appearance and manufacturability of the design. In addition, Autorouter is an orthogonal router and creates 90 degrees corners; glossing converts the corners to 45 degrees.


A suite of nine glossing functions are accessible from the Glossing Controller form, which lets you edit their parameters, listed below, and control their execution.


The gloss routines can be run on an entire design, individual areas of the design, or individual nets on a design.


Note: You can exclude nets from glossing by assigning the NO_GLOSS or FIXED properties. Similarly, exclude areas from glossing by assigning the NO_GLOSS_TOP, BOTTOM, INTERNAL properties.


To gloss the design, perform the following steps:

1. Choose Route — Gloss —Parameters.
2. Select to run Line and via cleanup, Line smoothing, Center lines between pads, and Improve line entry into pads, as shown in the following figure.


Note: The availability of glossing application depends on the license you are using. See Reference section for more details.


3. Click Gloss.


To learn more about the glossing applications, see:


  • The Post-route Clean Up chapter of the Allegro User Guide: Routing the Design manual
  • The gloss param section of the Allegro PCB and Physical Layout Command Reference: P Commands manual


Delay Tuning


Nets containing minimum propagation delay, minimum total etch, or relative delay rules often require additional compensation etch to meet these respective constraint conditions.


You can use either the Delay Tune option or the Auto-interactive Delay Tune option from the Route menu to generate tuning patterns. Using the Auto Interactive Delay Tune (AiDT) command you can interactively select clines or cline segments for tuning. AiDT computes the required length for the cline to meet timing constraints and utilizes controlled push/shove techniques while adding tuning patterns based on parameters defined.


To add the Accordion tuning pattern using AiDT, do the following steps:


1. Choose Route — Auto-interactive Delay Tune.
2. Specify the Options Pane parameters, as shown in the following figure.


3. Click the cline or cline segment to tune. In the following figure, the top image shows a signal before and the bottom image shows the same net after tuning with an Accordion pattern.


For this tuning, an electrical CSet was added for propagation delay to add a delay of 20us. To add the constraint in Constraint Manager, select Min/Max Propagation Delays under Routing in the Electrical Constraint Set folder of the Electrical pane and then right-click the design name and choose Create — Electrical CSet. To assign the CSet to a net, select Min/Max Propagation Delays in the Routing folder under Net and then assign the CSet to the net by selecting the CSet from the Referenced Electrical CSet cell.



To learn more about delay tuning, see:


  • The Delay Tuning section of the Allegro User Guide: Routing the Design manual
  • Allegro User Guide: Allegro Timing Environment


Adding a Dynamic Shape


In the layout tools, shapes comprise bounded areas of conductor on etch/conductor layers that are solid-filled or crosshatched with conducting etch/conductor (usually copper). You use etch/conductor shapes as shielding around components or as pads that are not one of the regular shapes (circle, rectangle, oblong), and to fill entire layers with conductor as voltage distribution (embedded) planes. You can add and edit positive shapes at any time in the design process, controlling when and how each shape’s fill is updated and voided.


A dynamic shape is one whose fill is automatically updated to execute connectivity, generate voids, and run design rule checking to produce artwork quality output. Its Dynamic Copper Fill mode is defined as Smooth on the Global Dynamic Shape Parameters dialog box. This means that no additional post processing is required on the shape. Use dynamic positive shapes as ground shielding on outer layers and as inner layer planes if current designs use positive static planes, and performance is acceptable.


To create a dynamic shape, say on the layer PWR1 for net IOVP, perform the following steps:

1. In the Options pane, select the class and subclass; for example, select Etch and PWR1.


2. Choose a shape type from the Shape menu, such as Rectangular or Polygon.

3. Specify the settings in the Options pane. For a dynamic shape, select Dynamic copper in the Type field under Shape Fill and specify the net in the Assign net name field.


4. Draw one or more shapes and choose Done from the pop-up menu when finished.



To learn more about shapes in general and dynamic shapes in particular, see:


  • The Layout Padstacks, Vias, and Etch/Conductor Shapes chapter of Allegro User Guide: Preparing the Layout
  • Best Practices: Working with Shapes


Preparing Artwork


Artwork is the film, usually mylar, which contains an accurately scaled representation of each layer of a printed circuit/substrate design. In the layout editor, creating artwork is the process of generating files that are used by the manufacturer to physically put the printed circuit design onto film.


The two artwork processes are vector-based and raster-based. Each uses a different generation of photoplotters. Both produce positive and negative artwork film. The layout editor supports both vector-based and raster-based photoplotter formats.


The conductor artwork elements are generated automatically, namely, Etch, Pin, and Via class. You can specify to generate nonconductor artwork elements, such as a soldermask or a silk screen.


You can use the Autosilk tool to generate the silkscreen. This tool defines the operating characteristics of the silkscreen program, letting you create composite silkscreen data on class MANUFACTURING and subclasses AUTOSILK_TOP and AUTOSILK_BOTTOM in your layout. It creates data for subclass AUTOSILK_TOP or AUTOSILK_BOTTOM or both, depending on how you set the Auto Silkscreen parameters.


To generate the silkscreen, perform the following steps:


1. Choose Manufacture — Silkscreen
2. Specify the classes and subclasses; for example, as shown in the following figure.


3. Click Silkscreen.


This will generate Manufacturing/Autosilk_Top and Manufacturing/Autosilk_Bottom.


To add a soldermask and a silkscreen for the top of the board in the Gerber RS274X format, perform the following steps:


1. Choose Manufacture — Artwork to open the Artwork Control Form.
2. Specify the general parameters as shown in the following figure.


1. Open Color dialog (Display — Color/Visibility)
2. Click Off for Global visibility.
3. Ensure that Soldermsk_Top and Silkscreen_Top are checked for Board Geometry and Package Geometry.


4. Click OK to apply changes and close Color Dialog.
5. In the File Control tab of Artwork Control Form, right-click any folder and choose Add.
6. Specify a name, say SilkScreenTop.
7. Similarly, specify a name for the soldermask, say SolderMaskTop.
8. Add the subclasses as shown in the following figure.


To add a subclass, select an item under the folder and choose Add from the pop- up menu to open the Subclass Selection window.


Note: Testprep creates test probe sites for any type of test fixture using parameters that enable you to control making test locations on a design. You can create testpoints automatically or interactively, as well as edit all testpoint locations. You can automatically choose and label appropriate component pin, via, or pad locations as testpoints. Once you finish generating testpoints, you can create artwork and NC data files for drilling design test beds. For more information, see the Test Preparation section of Allegro User Guide: Preparing Manufacturing Data.


Note: Generating Artwork can be followed by numerical control (NC) output by using the NC drill environment. For more information, see the Working with the NC Drill Environment manual and the Creating Numerical Control Data section of Allegro User Guide: Preparing Manufacturing Data.




To learn more about manufacturing tasks in PCB Editor, see:

  • Allegro User Guide: Preparing Manufacturing Data
  • The silkscreen param section of the Allegro PCB and Physical Layout Command Reference: S Commands manual